Patents by Inventor Tae Tawara

Tae Tawara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11183590
    Abstract: A semiconductor device including a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, provided at a front surface of the semiconductor substrate and having an impurity concentration lower than that of the semiconductor substrate, a second semiconductor layer of a second conductivity type, selectively provided on the first semiconductor layer, a first semiconductor region of the first conductivity type, selectively provided in the second semiconductor layer and having an impurity concentration higher than that of the semiconductor substrate, a trench penetrating the first semiconductor region and the second semiconductor layer, to reach the first semiconductor layer, and a gate electrode provided in the trench, via a gate insulating film. The trench has a sidewall that includes a terrace portion, surface roughness of the terrace portion being at most 0.1 nm.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: November 23, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Tae Tawara, Shinji Fujikake, Aki Takigawa, Hidekazu Tsuchida, Koichi Murata
  • Publication number: 20210074850
    Abstract: A semiconductor device including a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, provided at a front surface of the semiconductor substrate and having an impurity concentration lower than that of the semiconductor substrate, a second semiconductor layer of a second conductivity type, selectively provided on the first semiconductor layer, a first semiconductor region of the first conductivity type, selectively provided in the second semiconductor layer and having an impurity concentration higher than that of the semiconductor substrate, a trench penetrating the first semiconductor region and the second semiconductor layer, to reach the first semiconductor layer, and a gate electrode provided in the trench, via a gate insulating film. The trench has a sidewall that includes a terrace portion, surface roughness of the terrace portion being at most 0.1 nm.
    Type: Application
    Filed: August 3, 2020
    Publication date: March 11, 2021
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Tae TAWARA, Shinji FUJIKAKE, Aki TAKIGAWA, Hidekazu TSUCHIDA, Koichi MURATA
  • Patent number: 7682991
    Abstract: A method of manufacturing a silicon carbide semiconductor device includes forming a trench for a MOS gate in an SiC substrate by dry etching. Thereafter, the substrate with the trench is heat treated. The heat treatment includes heating the substrate in an Ar gas atmosphere or in a mixed gas atmosphere containing SiH4 and Ar at a temperature between 1600° C. and 1800° C., and thereafter in a hydrogen gas atmosphere at a temperature between 1400° C. and 1500° C. The present manufacturing method smoothens the trench inner surface and rounds the corners in the trench to prevent the electric field from localizing thereto.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: March 23, 2010
    Assignee: Fuji Electric Device Technology Co., Ltd.
    Inventors: Yasuyuki Kawada, Takeshi Tawara, Tae Tawara
  • Publication number: 20080220620
    Abstract: A method of manufacturing a silicon carbide semiconductor device includes forming a trench for a MOS gate in an SiC substrate by dry etching. Thereafter, the substrate with the trench is heat treated. The heat treatment includes heating the substrate in an Ar gas atmosphere or in a mixed gas atmosphere containing SiH4 and Ar at a temperature between 1600° C. and 1800° C., and thereafter in a hydrogen gas atmosphere at a temperature between 1400° C. and 1500° C. The present manufacturing method smoothens the trench inner surface and rounds the corners in the trench to prevent the electric field from localizing thereto.
    Type: Application
    Filed: December 19, 2007
    Publication date: September 11, 2008
    Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.
    Inventors: Yasuyuki KAWADA, Takeshi TAWARA, Tae Tawara