Abstract: The present technology relates to a memory device and a method of operating the memory device. The memory device includes a memory block including a plurality of memory cells corresponding to a plurality of word line groups, a source line driver configured to apply an erase voltage to a source line of the memory block during an erase operation, a voltage generation circuit configured to apply an operation voltage increasing from a first operation voltage to a second operation voltage to the plurality of word line groups during the erase operation, and a control logic configured to control the source line driver and the voltage generation circuit to perform a suspend operation of stopping the erase operation.

Abstract: Provided herein is a method of measuring a refractive index of a semiconductor memory device and a method of classifying a product group of a semiconductor memory device using the same. The method of measuring a refractive index of a semiconductor memory device includes measuring a positive breakdown voltage and a negative breakdown voltage of each of memory cells coupled to a selected word line. The method also includes checking a refractive index of a charge storage layer of each of the memory cells based on the measured positive breakdown voltage and the measured negative breakdown voltage.

Abstract: A reliability measuring apparatus includes an oxide-nitride-oxide-alumina (ONOA) current measuring circuit configured to measure an ONOA current by applying an ONOA current measuring voltage to a selected word line coupled to a selected memory cell in a flash memory and a reliability indicator generator configured to a reliability indicator using the ONOA current measured through the measuring circuit.

Abstract: The present technology relates to a memory device and a method of operating the memory device. The memory device includes a memory block including a plurality of memory cells corresponding to a plurality of word line groups, a source line driver configured to apply an erase voltage to a source line of the memory block during an erase operation, a voltage generation circuit configured to apply an operation voltage increasing from a first operation voltage to a second operation voltage to the plurality of word line groups during the erase operation, and a control logic configured to control the source line driver and the voltage generation circuit to perform a suspend operation of stopping the erase operation.

Abstract: A memory device includes a memory cell array and a peripheral circuit. The memory cell array includes a plurality of memory blocks. The peripheral circuit performs a dummy operation on a dummy area among the plurality of memory blocks of the memory cell array.

Abstract: A memory device includes a memory cell array and a peripheral circuit. The memory cell array includes a plurality of memory blocks. The peripheral circuit performs a dummy operation on a dummy area among the plurality of memory blocks of the memory cell array.

Abstract: A non-volatile memory device and a read method thereof are disclosed. The read method includes providing a memory block having memory cells connected to word lines and connected in serial to a bit line, sensing potential of the bit line by applying a first read voltage to a selected word line of the word lines and providing a first pass voltage to an unselected word line adjacent to the selected word line, sensing potential of the bit line by applying a second read voltage higher than the first read voltage to the selected word line and providing a second pass voltage lower than the first pass voltage to the unselected word line adjacent to the selected word line, and sensing potential of the bit line by applying a third read voltage higher than the second read voltage to the selected word line and providing a third pass voltage lower than the second pass voltage to the unselected word line adjacent to the selected word line.

Abstract: The present invention discloses a method of fabricating a semiconductor memory device including forming sequentially a gate insulating layer and a first conductive pattern on a semiconductor substrate; forming a protective layer on surfaces of the first conductive pattern and the gate insulating layer; performing an etching process to form a trench, the etching process being performed such that the protective layer remains on side walls of the first conductive pattern to form a protective pattern; forming an isolation layer in the trench; etching the isolation layer; removing the protective pattern above a surface of the isolation layer; and forming sequentially a dielectric layer and a second conductive layer on surfaces of the isolation layer, the protective pattern and the first conductive pattern.

Abstract: A non-volatile memory device includes a memory cell block programmed with data, a page buffer block configured to perform a program verification operation for verifying the data on a verification target memory cell as many times as a predetermined number, and temporarily store a plurality of verification result data obtained from every program verification operation, a comparison block configured to compare the multiple verification result data, which are temporarily stored in the page buffer block, with each other to produce a comparison result, and a control block configured to determine whether a program operation is performed again on the verification target memory cell based on the comparison result.

Abstract: A non-volatile memory device and a read method thereof are disclosed. The read method includes providing a memory block having memory cells connected to word lines and connected in serial to a bit line, sensing potential of the bit line by applying a first read voltage to a selected word line of the word lines and providing a first pass voltage to an unselected word line adjacent to the selected word line, sensing potential of the bit line by applying a second read voltage higher than the first read voltage to the selected word line and providing a second pass voltage lower than the first pass voltage to the unselected word line adjacent to the selected word line, and sensing potential of the bit line by applying a third read voltage higher than the second read voltage to the selected word line and providing a third pass voltage lower than the second pass voltage to the unselected word line adjacent to the selected word line.

Abstract: The present invention discloses a method of fabricating a semiconductor memory device including forming sequentially a gate insulating layer and a first conductive pattern on a semiconductor substrate; forming a protective layer on surfaces of the first conductive pattern and the gate insulating layer; performing an etching process to form a trench, the etching process being performed such that the protective layer remains on side walls of the first conductive pattern to form a protective pattern; forming an isolation layer in the trench; etching the isolation layer; removing the protective pattern above a surface of the isolation layer; and forming sequentially a dielectric layer and a second conductive layer on surfaces of the isolation layer, the protective pattern and the first conductive pattern.

Abstract: A nonvolatile memory device can improve its operation characteristic by reducing leakage current of a bit line in a read operation. The nonvolatile memory device includes a plurality of word lines, a plurality of main bit lines intersecting with the plurality of word lines, a plurality of cell blocks each including a plurality of cell strings, each of the cell strings including first and second select transistors and a plurality of memory cells, a plurality of sub bit lines commonly connected to the respective cell strings in same group, the cell blocks being grouped into a plurality of groups whose number is identical to or smaller than the number of the cell blocks, a plurality of group selectors configured to selectively connect the main bit lines to the sub bit lines of a selected group, and a plurality of page buffers configured to sense data of the memory cells through the main bit lines.

Abstract: The present invention discloses a method of fabricating a semiconductor memory device including forming sequentially a gate insulating layer and a first conductive pattern on a semiconductor substrate; forming a protective layer on surfaces of the first conductive pattern and the gate insulating layer; performing an etching process to form a trench, the etching process being performed such that the protective layer remains on side walls of the first conductive pattern to form a protective pattern; forming an isolation layer in the trench; etching the isolation layer; removing the protective pattern above a surface of the isolation layer; and forming sequentially a dielectric layer and a second conductive layer on surfaces of the isolation layer, the protective pattern and the first conductive pattern.

Abstract: A nonvolatile memory device can improve its operation characteristic by reducing leakage current of a bit line in a read operation. The nonvolatile memory device includes a plurality of word lines, a plurality of main bit lines intersecting with the plurality of word lines, a plurality of cell blocks each including a plurality of cell strings, each of the cell strings including first and second select transistors and a plurality of memory cells, a plurality of sub bit lines commonly connected to the respective cell strings in same group, the cell blocks being grouped into a plurality of groups whose number is identical to or smaller than the number of the cell blocks, a plurality of group selectors configured to selectively connect the main bit lines to the sub bit lines of a selected group, and a plurality of page buffers configured to sense data of the memory cells through the main bit lines.

Abstract: A NAND flash memory device, and more particularly, to NAND flash memory device and method of manufacturing operating the same as described. A dielectric film and a conduction layer are formed between cell gates so that between-cell gates are buried. Therefore, an interference effect between floating gates, which becomes profound with the level of integration increasing, and program threshold voltage distributions between cells can be improved.