Abstract: Provided is an operating method of a processing circuit, the method including generating a first compressed chunk including only a first valid value, generating a first mask includes a reference value at a same position as a position of the first valid value, and includes a plurality of first sub-masks, generating a second compressed chunk including only a second valid value, generating a second mask, includes a reference value at a same position as a position of the second valid value, and includes a plurality of second sub-masks, generating a valid pair position value for each of a current first sub-mask and a current second sub-mask, generating a first cumulative value corresponding to a number of reference values included in a first previous sub-mask, and generating a second cumulative value corresponding to a number of reference values included in a second previous sub-mask.

Abstract: Provided are a quantization method and a quantization apparatus for an artificial neural network. The quantization method for the artificial neural network may include estimating sample scale factors of first sample parameters that are part of first parameters within the artificial neural network, determining a prediction scale factor based on the sample scale factors, and quantizing first parameters based on the prediction scale factor.

Abstract: Disclosed is a processor for performing a speculative execution for an out-of-order execution. The processor may include: a core; and an L1 cache memory, and the core may include a speculative track buffer (STB) storing speculative track information in order to track the speculative instruction when a speculative instruction is recorded in a reorder buffer (ROB), and a load queue (LQ) transmitting a commit doorbell signal or a restore doorbell signal for a first speculative block to which a first speculative instruction belongs to an L1 cache memory based on first speculative track information of the first speculative instruction when a speculative success or a speculative failure of the first speculative instruction included in the speculative instruction is decided, and the L1 cache memory may include a write buffer.

Abstract: Disclosed is a continual learning method for a deep learning model. The continual learning method of the deep learning model is performed by a computing device including at least a processor and, for continual learning for a second task and an nth task for the deep learning model trained for a first task, includes a forward propagation operation of performing a forward propagation; a backward propagation operation of performing a backward propagation; and a weight update operation of performing a weight update, wherein the forward propagation operation, the backward propagation operation, and the weight update operation are repeatedly performed, and the update operation is performed based on an activation tendency of each of neurons included in the deep learning model, in a process in which training for the first task proceeds.

Abstract: Disclosed is a processor for performing a speculative execution for an out-of-order execution. The processor may include: a core; and an L1 cache memory, and the core may include a speculative track buffer (STB) storing speculative track information in order to track the speculative instruction when a speculative instruction is recorded in a reorder buffer (ROB), and a load queue (LQ) transmitting a commit doorbell signal or a restore doorbell signal for a first speculative block to which a first speculative instruction belongs to an L1 cache memory based on first speculative track information of the first speculative instruction when a speculative success or a speculative failure of the first speculative instruction included in the speculative instruction is decided, and the L1 cache memory may include a write buffer.

Abstract: Disclosed is a method of operating an immediate value in an extendable instruction set computer (EISC) processor, comprising: checking whether or not an unsigned immediate value is used to generate an extension register (ER) value for operating an immediate value; and generating the ER value by performing zero extension for the unsigned immediate value using an unsigned load extension register with immediate (ULERI) instruction if the unsigned immediate value is used. It is possible to improve operational efficiency by preventing an LERI instruction from being unnecessarily executed when an immediate value is operated using a 16-bit instruction in the EISC processor.