Abstract: Disclosed is a processor for performing a speculative execution for an out-of-order execution. The processor may include: a core; and an L1 cache memory, and the core may include a speculative track buffer (STB) storing speculative track information in order to track the speculative instruction when a speculative instruction is recorded in a reorder buffer (ROB), and a load queue (LQ) transmitting a commit doorbell signal or a restore doorbell signal for a first speculative block to which a first speculative instruction belongs to an L1 cache memory based on first speculative track information of the first speculative instruction when a speculative success or a speculative failure of the first speculative instruction included in the speculative instruction is decided, and the L1 cache memory may include a write buffer.

Abstract: Disclosed is a method of operating an immediate value in an extendable instruction set computer (EISC) processor, comprising: checking whether or not an unsigned immediate value is used to generate an extension register (ER) value for operating an immediate value; and generating the ER value by performing zero extension for the unsigned immediate value using an unsigned load extension register with immediate (ULERI) instruction if the unsigned immediate value is used. It is possible to improve operational efficiency by preventing an LERI instruction from being unnecessarily executed when an immediate value is operated using a 16-bit instruction in the EISC processor.