Patents by Inventor Tae-Won Ha

Tae-Won Ha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11581435
    Abstract: A semiconductor device includes a substrate including a first active region, a second active region and a field region between the first and second active regions, and a gate structure formed on the substrate to cross the first active region, the second active region and the field region. The gate structure includes a p type metal gate electrode and an n-type metal gate electrode directly contacting each other, the p-type metal gate electrode extends from the first active region less than half way toward the second active region.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: February 14, 2023
    Inventors: Ju-Youn Kim, Hyung-Soon Jang, Jong-Mil Youn, Tae-Won Ha
  • Publication number: 20200303547
    Abstract: A semiconductor device includes a substrate including a first active region, a second active region and a field region between the first and second active regions, and a gate structure formed on the substrate to cross the first active region, the second active region and the field region. The gate structure includes a p type metal gate electrode and an n-type metal gate electrode directly contacting each other, the p-type metal gate electrode extends from the first active region less than half way toward the second active region.
    Type: Application
    Filed: June 8, 2020
    Publication date: September 24, 2020
    Inventors: Ju-Youn Kim, Hyung-Soon Jang, Jong-Mil Youn, Tae-Won Ha
  • Patent number: 10714614
    Abstract: A semiconductor device includes a substrate including a first active region, a second active region and a field region between the first and second active regions, and a gate structure formed on the substrate to cross the first active region, the second active region and the field region. The gate structure includes a p type metal gate electrode and an n-type metal gate electrode directly contacting each other, the p-type metal gate electrode extends from the first active region less than half way toward the second active region.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: July 14, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ju-Youn Kim, Hyung-Soon Jang, Jong-Mil Youn, Tae-Won Ha
  • Patent number: 10580891
    Abstract: A semiconductor device capable of adjusting profiles of a gate electrode and a gate spacer by implanting or doping an element semiconductor material into an interlayer insulating layer may be provided. The semiconductor device may include a gate spacer on a substrate, the gate spacer defining a trench, a gate electrode filling the trench, and an interlayer insulating layer on the substrate, which surrounds the gate spacer, and at least a portion of which includes germanium.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: March 3, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Soo Kim, Gi-Gwan Park, Sang-Koo Kang, Koung-Min Ryu, Jae-Hoon Lee, Tae-Won Ha
  • Publication number: 20190088779
    Abstract: A semiconductor device capable of adjusting profiles of a gate electrode and a gate spacer by implanting or doping an element semiconductor material into an interlayer insulating layer may be provided. The semiconductor device may include a gate spacer on a substrate, the gate spacer defining a trench, a gate electrode filling the trench, and an interlayer insulating layer on the substrate, which surrounds the gate spacer, and at least a portion of which includes germanium.
    Type: Application
    Filed: November 16, 2018
    Publication date: March 21, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sung-Soo KIM, Gi-Gwan PARK, Sang-Koo KANG, Koung-Min RYU, Jae-Hoon LEE, Tae-Won HA
  • Patent number: 10177253
    Abstract: A semiconductor device capable of adjusting profiles of a gate electrode and a gate spacer by implanting or doping an element semiconductor material into an interlayer insulating layer may be provided. The semiconductor device may include a gate spacer on a substrate, the gate spacer defining a trench, a gate electrode filling the trench, and an interlayer insulating layer on the substrate, which surrounds the gate spacer, and at least a portion of which includes germanium.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: January 8, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Soo Kim, Gi-Gwan Park, Sang-Koo Kang, Koung-Min Ryu, Jae-Hoon Lee, Tae-Won Ha
  • Publication number: 20180366582
    Abstract: A semiconductor device includes a substrate including a first active region, a second active region and a field region between the first and second active regions, and a gate structure formed on the substrate to cross the first active region, the second active region and the field region. The gate structure includes a p type metal gate electrode and an n-type metal gate electrode directly contacting each other, the p-type metal gate electrode extends from the first active region less than half way toward the second active region.
    Type: Application
    Filed: August 22, 2018
    Publication date: December 20, 2018
    Inventors: Ju-Youn Kim, Hyung-Soon Jang, Jong-Mil Youn, Tae-Won Ha
  • Patent number: 10084088
    Abstract: A semiconductor device includes a substrate including a first active region, a second active region and a field region between the first and second active regions, and a gate structure formed on the substrate to cross the first active region, the second active region and the field region. The gate structure includes a p type metal gate electrode and an n-type metal gate electrode directly contacting each other, the p-type metal gate electrode extends from the first active region less than half way toward the second active region.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: September 25, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ju-Youn Kim, Hyung-Soon Jang, Jong-Mil Youn, Tae-Won Ha
  • Patent number: 9812367
    Abstract: A method of fabricating a semiconductor device includes forming an inter-metal dielectric layer including a first trench and a second trench which are spaced from each other on a substrate, forming a first dielectric layer along the sides and bottom of the first trench, forming a second dielectric layer along the sides and bottom of the second trench, forming first and second lower conductive layers on the first and second dielectric layers, respectively, forming first and second capping layers on the first and second lower conductive layer, respectively, performing a heat treatment after the first and second capping layers have been formed, removing the first and second capping layers and the first and second lower conductive layers after performing the heat treatment, and forming first and second metal gate structures on the first and second dielectric layers, respectively.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: November 7, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ju-Youn Kim, Ji-Hwan An, Kwang-Yul Lee, Tae-Won Ha, Jeong-Nam Han
  • Publication number: 20170278966
    Abstract: A semiconductor device includes a substrate including a first active region, a second active region and a field region between the first and second active regions, and a gate structure formed on the substrate to cross the first active region, the second active region and the field region. The gate structure includes a p type metal gate electrode and an n-type metal gate electrode directly contacting each other, the p-type metal gate electrode extends from the first active region less than half way toward the second active region.
    Type: Application
    Filed: June 9, 2017
    Publication date: September 28, 2017
    Inventors: Ju-Youn Kim, Hyung-Soon Jang, Jong-Mil Youn, Tae-Won Ha
  • Patent number: 9698264
    Abstract: A semiconductor device includes a substrate including a first active region, a second active region and a field region between the first and second active regions, and a gate structure formed on the substrate to cross the first active region, the second active region and the field region. The gate structure includes a p type metal gate electrode and an n-type metal gate electrode directly contacting each other, the p-type metal gate electrode extends from the first active region less than half way toward the second active region.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: July 4, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ju-Youn Kim, Hyung-Soon Jang, Jong-Mil Youn, Tae-Won Ha
  • Publication number: 20170117192
    Abstract: A semiconductor device may include a first gate electrode being formed on a substrate and having a first ratio of a width of an upper surface to a width of a lower surface, a second gate electrode being formed on the substrate and having a second ratio of the width of the upper surface to the width of the lower surface, wherein the second ratio is less than the first ratio, a first gate spacer being formed on a sidewall of the first gate electrode, a second gate spacer being formed on a sidewall of the second gate electrode and an interlayer insulating film covering the first gate spacer and the second gate spacer.
    Type: Application
    Filed: July 21, 2016
    Publication date: April 27, 2017
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sun-Ki Min, Gi-Gwan PARK, Sang-Koo KANG, Sung-Sao KIM, Ju-Youn KIM, Koung-Min RYU, Jae-Hoon LEE, Tae-Won HA
  • Publication number: 20170110576
    Abstract: A semiconductor device capable of adjusting profiles of a gate electrode and a gate spacer by implanting or doping an element semiconductor material into an interlayer insulating layer may be provided. The semiconductor device may include a gate spacer on a substrate, the gate spacer defining a trench, a gate electrode filling the trench, and an interlayer insulating layer on the substrate, which surrounds the gate spacer, and at least a portion of which includes germanium.
    Type: Application
    Filed: October 11, 2016
    Publication date: April 20, 2017
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sung-Soo KIM, Gi-Gwan PARK, Sang-Koo KANG, Koung-Min RYU, Jae-Hoon LEE, Tae-Won HA
  • Patent number: 9515182
    Abstract: A semiconductor device includes a substrate including a first active region, a second active region and a field region between the first and second active regions, and a gate structure formed on the substrate to cross the first active region, the second active region and the field region. The gate structure includes a p type metal gate electrode and an n-type metal gate electrode directly contacting each other, the p-type metal gate electrode extends from the first active region less than half way toward the second active region.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: December 6, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ju-Youn Kim, Hyung-Soon Jang, Jong-Mil Youn, Tae-Won Ha
  • Patent number: 9502417
    Abstract: A semiconductor device includes a substrate including a first active region, a second active region and a field region between the first and second active regions, and a gate structure formed on the substrate to cross the first active region, the second active region and the field region. The gate structure includes a p type metal gate electrode and an n-type metal gate electrode directly contacting each other, the p-type metal gate electrode extends from the first active region less than half way toward the second active region.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: November 22, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ju-Youn Kim, Hyung-Soon Jang, Jong-Mil Youn, Tae-Won Ha
  • Patent number: 9461173
    Abstract: A semiconductor device includes a substrate including a first active region, a second active region and a field region between the first and second active regions, and a gate structure formed on the substrate to cross the first active region, the second active region and the field region. The gate structure includes a p type metal gate electrode and an n-type metal gate electrode directly contacting each other, the p-type metal gate electrode extends from the first active region less than half way toward the second active region.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: October 4, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ju-Youn Kim, Hyung-Soon Jang, Jong-Mil Youn, Tae-Won Ha
  • Publication number: 20160163706
    Abstract: A semiconductor device includes a substrate including a first active region, a second active region and a field region between the first and second active regions, and a gate structure formed on the substrate to cross the first active region, the second active region and the field region. The gate structure includes a p type metal gate electrode and an n-type metal gate electrode directly contacting each other, the p-type metal gate electrode extends from the first active region less than half way toward the second active region.
    Type: Application
    Filed: February 18, 2016
    Publication date: June 9, 2016
    Inventors: Ju-Youn Kim, Hyung-Soon Jang, Jong-Mil Youn, Tae-Won Ha
  • Publication number: 20160126351
    Abstract: A semiconductor device includes a substrate including a first active region, a second active region and a field region between the first and second active regions, and a gate structure formed on the substrate to cross the first active region, the second active region and the field region. The gate structure includes a p type metal gate electrode and an n-type metal gate electrode directly contacting each other, the p-type metal gate electrode extends from the first active region less than half way toward the second active region.
    Type: Application
    Filed: January 8, 2016
    Publication date: May 5, 2016
    Inventors: Ju-Youn Kim, Hyung-Soon Jang, Jong-Mil Youn, Tae-Won Ha
  • Publication number: 20160111428
    Abstract: A semiconductor device includes a substrate including a first active region, a second active region and a field region between the first and second active regions, and a gate structure formed on the substrate to cross the first active region, the second active region and the field region. The gate structure includes a p type metal gate electrode and an n-type metal gate electrode directly contacting each other, the p-type metal gate electrode extends from the first active region less than half way toward the second active region.
    Type: Application
    Filed: December 16, 2015
    Publication date: April 21, 2016
    Inventors: Ju-Youn Kim, Hyung-Soon Jang, Jong-Mil Youn, Tae-Won Ha
  • Publication number: 20160093620
    Abstract: A semiconductor device includes a substrate including a first active region, a second active region and a field region between the first and second active regions, and a gate structure formed on the substrate to cross the first active region, the second active region and the field region. The gate structure includes a p type metal gate electrode and an n-type metal gate electrode directly contacting each other, the p-type metal gate electrode extends from the first active region less than half way toward the second active region.
    Type: Application
    Filed: December 10, 2015
    Publication date: March 31, 2016
    Inventors: Ju-Youn Kim, Hyung-Soon Jang, Jong-Mil Youn, Tae-Won Ha