Patents by Inventor Tae Woo Oh

Tae Woo Oh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250064879
    Abstract: The present invention relates to a composition for treating, improving, or preventing Alzheimer's disease caused by ApoE4 gene mutation, the composition including Banha-Sasim-Tang as an active ingredient. The composition including Banha-Sasim-Tang as an active ingredient of the present invention and a treatment method exhibit excellent effects of reducing amyloid beta proteins and inhibiting deposition thereof, which are specific to Alzheimer's disease caused by ApoE4 gene mutation, thereby having high applicability as a specific composition for preventing, improving, or treating Alzheimer's disease caused by ApoE4 gene mutation.
    Type: Application
    Filed: September 30, 2022
    Publication date: February 27, 2025
    Inventors: Younghoon GO, Buyun KIM, Jae Kwang KIM, Jang-Gi CHOI, Tae Woo OH, Malk Eun PAK, Yeo Jin PARK, Jinsoo SEO, Hyein LEE
  • Patent number: 12087344
    Abstract: Exemplary embodiments provide a sensing amplifier based flip-flop applying a nonvolatile memory device which is applicable to a mobile device which has a small hardware area, uses a small control signal, does not include a separate write circuit, has low writing power consumption, a short reading time and small power consumption, and requires a low power operation.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: September 10, 2024
    Assignee: UIF (University Industry Foundation), Yonsei University
    Inventors: Seong Ook Jung, Se Keon Kim, Tae Woo Oh, Se Hee Lim, Dong Han Ko
  • Patent number: 11955155
    Abstract: A nonvolatile memory device according to the embodiment includes: a first inverter; and a second inverter cross-coupled to the first inverter, wherein the second inverter includes a pull-up transistor, a pull-down transistor, and a ferroelectric field effect transistor having gate nodes connected to each other, and a restore transistor having one electrode connected to the ferroelectric field effect transistor, and the second inverter stores data in a nonvolatile manner.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: April 9, 2024
    Assignee: UIF (UNIVERSITY INDUSTRY FOUNDATION), YONSEI UNIVERSITY
    Inventors: Seong Ook Jung, Se Keon Kim, Tae Woo Oh, Se Hee Lim, Dong Han Ko
  • Patent number: 11955157
    Abstract: A PUF apparatus comprises: a PUF cell array in which a plurality of PUF cells are arranged each including a FeFET pair whose gates are commonly connected to a corresponding word line among a plurality of word lines, and whose drains and sources are connected to a corresponding bit line pair and a corresponding source line pair among a plurality of bit line pairs and a plurality of source line pairs running in a direction crossing the plurality of word lines; and a read-write-back block which is activated according to a read enable signal, and senses and amplifies a voltage difference occurring in a corresponding bit line pair among the plurality of bit line pairs according to the difference in driving strength due to a deviation in a manufacturing process of the FeFET pair in the PUF cell selected by a selected word line among the plurality of word lines.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: April 9, 2024
    Assignee: INDUSTRY-ACADEMIC CORPORATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Seong Ook Jung, Se Hee Lim, Tae Woo Oh, Se Keon Kim, Dong Han Ko
  • Publication number: 20240072787
    Abstract: Disclosed are a circuit and a system which is capable of improving reliability by preventing destructive overvoltage that occurs in an element using a low power supply voltage when various signals are transmitted from an integrated circuit with a high power supply voltage to an integrated circuit with a low power supply voltage.
    Type: Application
    Filed: February 2, 2023
    Publication date: February 29, 2024
    Applicant: Haechitech Corporation
    Inventors: Tae Woo OH, Sung Keun LEE
  • Publication number: 20230344418
    Abstract: Disclosed are a circuit and a system which prevent unnecessary power consumption by cutting off static current occurring when a signal is transmitted from an integrated circuit with a low power supply voltage to an integrated circuit with a high power supply voltage.
    Type: Application
    Filed: February 2, 2023
    Publication date: October 26, 2023
    Applicant: Haechitech Corporation
    Inventors: Tae Woo OH, Hyung Il KIM
  • Patent number: 11790971
    Abstract: A ferroelectric random access memory device comprises: a memory cell array including a plurality of memory cells each having one ferroelectric transistor (FeFET) connected between a read line of a plurality of read lines and a source line of a plurality of source lines and one transistor connected between a bit line of a plurality of bit lines and a gate of the FeFET and having a gate connected to a corresponding word line of a plurality of word lines; and a read/write control unit, when address information for a memory cell to be written is applied with a write command and data, selecting a word line and a read line corresponding to a row address and applying a write voltage having a positive voltage level, and applying a ground voltage to the selected read line, and applying the write voltage to a bit line corresponding to a memory cell.
    Type: Grant
    Filed: January 4, 2022
    Date of Patent: October 17, 2023
    Assignee: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Seong Ook Jung, Dong Han Ko, Tae Woo Oh, Se Hee Lim, Se Keon Kim
  • Publication number: 20230070525
    Abstract: Provided are a system and method for work quality assurance in vehicle manufacturing, which are capable of preventing defects in manufacturing, wherein the system for work quality assurance in vehicle manufacturing which assembles fastening objects to a vehicle transferred through a conveyor line through a working unit, includes a server configured to set a working area of the vehicle, assign work corresponding to the working area, check a position of the working unit in real time to calculate a stay period during which the working unit stays in the working area, receive work information from the working unit, and determine whether the work is successful on the basis of the stay period, the assigned work, and the work information.
    Type: Application
    Filed: September 8, 2022
    Publication date: March 9, 2023
    Applicant: TEIA Co., Ltd.
    Inventors: CHOONJAE LEE, BYEONGHEE YOUN, SANG WOOK PARK, TAE WOO OH
  • Patent number: 11564962
    Abstract: The present invention relates to a pharmaceutical composition comprising a maple leaf extract or fraction thereof for preventing or treating a retinal disease, a method for preventing or treating a retinal disease using the pharmaceutical composition, and a food composition comprising a maple leaf extract or fraction thereof for ameliorating the symptoms of a retinal disease. The pharmaceutical composition according to the present invention, which is effective for the treatment of a retinal disease, can be used pharmaceutically as a composition for preventing or treating a retinal disease, and can also be used advantageously as a health functional food.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: January 31, 2023
    Assignee: KOREA INSTITUTE OF ORIENTAL MEDICINE
    Inventors: Jin Yeul Ma, Kwang Il Park, Yeoun-Hee Kim, Tae Woo Oh, Won Kyung Cho, Dong-Gun Kim, Eun Hee Park
  • Publication number: 20220383926
    Abstract: Exemplary embodiments provide a sensing amplifier based flip-flop applying a nonvolatile memory device which is applicable to a mobile device which has a small hardware area, uses a small control signal, does not include a separate write circuit, has low writing power consumption, a short reading time and small power consumption, and requires a low power operation.
    Type: Application
    Filed: June 17, 2022
    Publication date: December 1, 2022
    Inventors: Seong Ook JUNG, Se Keon KIM, Tae Woo OH, Se Hee LIM, Dong Han KO
  • Publication number: 20220383927
    Abstract: A PUF apparatus comprises: a PUF cell array in which a plurality of PUF cells are arranged each including a FeFET pair whose gates are commonly connected to a corresponding word line among a plurality of word lines, and whose drains and sources are connected to a corresponding bit line pair and a corresponding source line pair among a plurality of bit line pairs and a plurality of source line pairs running in a direction crossing the plurality of word lines; and a read-write-back block which is activated according to a read enable signal, and senses and amplifies a voltage difference occurring in a corresponding bit line pair among the plurality of bit line pairs according to the difference in driving strength due to a deviation in a manufacturing process of the FeFET pair in the PUF cell selected by a selected word line among the plurality of word lines.
    Type: Application
    Filed: February 14, 2022
    Publication date: December 1, 2022
    Inventors: Seong Ook JUNG, Se Hee LIM, Tae Woo OH, Se Keon KIM, Dong Han KO
  • Publication number: 20220254398
    Abstract: A nonvolatile memory device according to the embodiment includes: a first inverter; and a second inverter cross-coupled to the first inverter, wherein the second inverter includes a pull-up transistor, a pull-down transistor, and a ferroelectric field effect transistor having gate nodes connected to each other, and a restore transistor having one electrode connected to the ferroelectric field effect transistor, and the second inverter stores data in a nonvolatile manner.
    Type: Application
    Filed: January 28, 2022
    Publication date: August 11, 2022
    Inventors: Seong Ook JUNG, Se Keon KIM, Tae Woo OH, Se Hee LIM, Dong Han KO
  • Publication number: 20220215870
    Abstract: A ferroelectric random access memory device comprises: a memory cell array including a plurality of memory cells each having one ferroelectric transistor (FeFET) connected between a read line of a plurality of read lines and a source line of a plurality of source lines and one transistor connected between a bit line of a plurality of bit lines and a gate of the FeFET and having a gate connected to a corresponding word line of a plurality of word lines; and a read/write control unit, when address information for a memory cell to be written is applied with a write command and data, selecting a word line and a read line corresponding to a row address and applying a write voltage having a positive voltage level, and applying a ground voltage to the selected read line, and applying the write voltage to a bit line corresponding to a memory cell.
    Type: Application
    Filed: January 4, 2022
    Publication date: July 7, 2022
    Inventors: Seong Ook JUNG, Dong Han KO, Tae Woo OH, Se Hee LIM, Se Keon KIM
  • Publication number: 20190328808
    Abstract: The present invention relates to a pharmaceutical composition comprising a maple leaf extract or fraction thereof for preventing or treating a retinal disease, a method for preventing or treating a retinal disease using the pharmaceutical composition, and a food composition comprising a maple leaf extract or fraction thereof for ameliorating the symptoms of a retinal disease. The pharmaceutical composition according to the present invention, which is effective for the treatment of a retinal disease, can be used pharmaceutically as a composition for preventing or treating a retinal disease, and can also be used advantageously as a health functional food.
    Type: Application
    Filed: August 11, 2017
    Publication date: October 31, 2019
    Inventors: Jin Yeul MA, Kwang Il PARK, Yeoun-Hee KIM, Tae Woo OH, Won Kyung CHO, Dong-Gun KIM, Eun Hee PARK
  • Patent number: 10319434
    Abstract: Disclosed is an SRAM cell capable of performing a differential operation. An SRAM cell according to an embodiment of the present disclosure may include a data node portion including four transistors constituting first and second data nodes; a data controller including first and second pass-gate transistors configured to control read and write of data in the first and second data nodes; and a control transistor connected to the data node portion through the second data node and configured to be controlled based on a driving voltage of a second word line having an opposite polarity to a first word line transmitting a driving voltage to the data controller.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: June 11, 2019
    Assignee: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Seong Ook Jung, Ju Hyun Park, Han Wool Jeong, Tae Woo Oh
  • Patent number: 10291211
    Abstract: Adaptive pulse generation circuits for clocking pulse latches with minimum hold time are provided. In one aspect, an adaptive pulse generation circuit employs a dynamic XOR-based logic gate configured to provide a pulse generation signal based on an XOR-based function of data input and data output-based signals of a pulse latch. A pull-down keeper circuit is configured to pull the pulse generation signal to a ground voltage in response to the pulse generation signal being in an inactive state while the clock signal is in an active state. A logic circuit is configured to generate an adaptive pulse signal to clock a pulse latch in response to the pulse generation signal and the clock signal being in an active state. This configuration results in the pulse width of the adaptive pulse signal corresponding to the input-to-output delay of the pulse latch.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: May 14, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Stanley Seungchul Song, Seong-Ook Jung, Hanwool Jeong, Tae Woo Oh, Giridhar Nallapati, Periannan Chidambaram
  • Publication number: 20180315472
    Abstract: Disclosed is an SRAM cell capable of performing a differential operation. An SRAM cell according to an embodiment of the present disclosure may include a data node portion including four transistors constituting first and second data nodes; a data controller including first and second pass-gate transistors configured to control read and write of data in the first and second data nodes; and a control transistor connected to the data node portion through the second data node and configured to be controlled based on a driving voltage of a second word line having an opposite polarity to a first word line transmitting a driving voltage to the data controller.
    Type: Application
    Filed: April 25, 2018
    Publication date: November 1, 2018
    Applicant: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Seong Ook JUNG, Ju Hyun PARK, Han Wool JEONG, Tae Woo OH
  • Patent number: 10020050
    Abstract: Provided is a local bit line-sharing memory device, including a plurality of memory cells that share a local bit line pair; a pre-charging unit that is connected to a write bit line pair and pre-charges the local bit line pair; and a data reading unit that reads data when bit line voltage pre-charged in a memory cell selected from the memory cells is discharged.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: July 10, 2018
    Assignee: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Seong-Ook Jung, Tae Woo Oh, Hanwool Jeong
  • Publication number: 20170309328
    Abstract: Disclosed is a local bit line-sharing memory device, including a plurality of memory cells that share a local bit line pair; a pre-charging unit that is connected to a write bit line pair and pre-charges the local bit line pair; and a data reading unit that reads data when bit line voltage pre-charged in a memory cell selected from the memory cells is discharged.
    Type: Application
    Filed: April 20, 2017
    Publication date: October 26, 2017
    Applicant: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Seong-Ook JUNG, Tae Woo OH, Hanwool JEONG
  • Patent number: 8553881
    Abstract: A composite masking system and method for improving the invisibility of high-definition video watermarking. The composite masking system includes a watermark generation module, a mask generation module, and watermark embedment means. The watermark generation module generates a basic watermark pattern using a private key, and generate a watermark pattern by repeatedly extending the basic watermark pattern. The mask generation module generates a Noise Visibility Function (NVF) mask using NVF masking means, an adaptive dithering mask using adaptive dithering masking means, and a contour mask using contour masking means. The watermark embedment means generates a composite mask by multiplying the NVF mask, the adaptive dithering mask and the contour mask together, multiplying the composite mask and the extended watermark pattern together, and embedding the result of the second multiplication in the luminance channel of an original image.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: October 8, 2013
    Assignee: Korea Advanced Institute of Science and Technology (KAIST)
    Inventors: Heung Kyu Lee, Tae Woo Oh, Kyung Su Kim, Ji Won Lee, Hee Dong Kim