Abstract: Disclosed is a method of playing a virtual reality image, and the method includes receiving, by a client, an image frame from a server, allocating the received image frame to a first layer, generating a second layer including at least one graphic user interface, composing the first layer and the second layer to generate a final image frame, and displaying the generated final image frame.

Abstract: The present invention relates to a display device having a touch detection function, and relates to a touch pad which is capable of detecting a contact touch and a contactless touch, a method of detecting a touch by using the same, and a display device including the same. According to the touch pad, the method of detecting a touch by using the touch pad, and the display device including the touch pad of the present invention, it is possible to simultaneously detect a contact touch and a contactless touch, and increase touch sensitivity by additionally applying a driving back voltage.

Abstract: In an embodiment of the present invention, a display device includes a display unit including a plurality of pixels, a first power supply unit configured to supply a first power voltage to the display unit, and a second power supply unit configured to cyclically supply a second power voltage to the display unit during a frame period.

Abstract: Disclosed is a high-speed track-and-hold device including a buffer stage circuit including a PMOS source follower and a post linear circuit, and a sampling stage circuit that is responsible for supplying a source voltage (VSS) to the buffer stage circuit and that is arranged so that a switch connected to a gate is connected to the source voltage (VSS) and the NMOS transistor of a sampling stage is turned off in hold operation.

Abstract: The present subject matter relates to the method of manufacturing circuit having lamination layer using LDS (Laser Direct Structuring) to ease the application on surface structure for applied product of various electronic circuit and particularly, in which can form circuit structure of single-layer to multiple-layer on the surface of injection-molded substrate in the shape of plane or curved surface, metal product, glasses, ceramic, rubber or other material.

Abstract: A fan-out semiconductor package includes: a core member including a support layer, a first wiring layer, a second wiring layer, and through-vias and having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant covering the core member and the semiconductor chip and filling at least portions of the through-hole; a connection member including an insulating layer disposed on the first wiring layer and the semiconductor chip, a redistribution layer disposed on the insulating layer, first vias electrically connecting the redistribution layer and the connection pads to each other, and second vias electrically connecting the redistribution layer and the first wiring layer to each other; and a passivation layer disposed on the insulating layer and covering the redistribution layer, wherein a thickness of the passivation layer is within half a distance from an inactive surface of the semiconductor chip to a lower surface of the encapsulant.

Abstract: A display device includes: a display panel including a plurality of pixels; a circuit board including: a power supply configured to output a reference voltage; and a signal controller; a connecting member electrically connecting the display panel and the circuit board; and a voltage modulator configured to generate a second power supply voltage of a low level with a division voltage using the reference voltage according to a switch control signal from the signal controller and to supply the second power supply voltage to the plurality of pixels.

Abstract: Disclosed herein is a secondary battery pack including an anode terminal and a cathode terminal of a battery cell connected to a protection circuit module (PCM), the anode terminal and the cathode terminal of the battery cell being made of plate-shaped conductive members, the battery cell having the anode terminal and the cathode terminal formed at one end thereof, the battery cell having a thermally bonded surplus part formed at the end thereof at which the anode terminal and the cathode terminal are formed, and the PCM including a protection circuit board (PCB) having a protection circuit formed thereon, an external input and output terminal connected to the protection circuit of the PCB, and an electrically insulative PCM case configured to have a hollow structure in which the PCB is mounted, the PCM case being provided with a slit, through which the electrode terminals of the battery cell are inserted, the PCM being loaded on the thermally bonded surplus part of the battery cell in a state in which the PC

Abstract: A battery pack which may secure safety when fire or gas occurs therein or when an external impact is applied thereto is provided. The battery pack includes: a cell assembly including a plurality of secondary batteries; and a pack case including a bottom part having a plate shape and located under the cell assembly, and a side wall part protruding from the bottom part to a preset height, the pack case accommodating the cell assembly in an inner space defined by the bottom part and the side wall part, wherein the side wall part of the pack case includes a hollow in a direction at least partially perpendicular to a thickness direction of the side wall part, and the hollow includes an inwardly open inlet and an outwardly open outlet.

Abstract: A semiconductor package includes a support member having first and second surfaces, having a cavity, and including a wiring structure, a semiconductor chip having connection pads, a connection member including a first insulating layer, a first redistribution layer on the first insulating layer, and a plurality of first vias connecting the wiring structure and the connection pads to the first redistribution layer and an encapsulant encapsulating the semiconductor chip, The wiring structure includes wiring patterns disposed on the second surface of the support member, and the first insulating layer includes a first insulating coating covering the wiring patterns and a second insulating coating disposed on the first insulating coating and having a higher level of flatness than that of the first insulating coating.

Abstract: A semiconductor package includes a support member having first and second surfaces opposing each other, including a cavity penetrating through the first and second surfaces, and having a primer layer disposed on the first surface; a connection member disposed on the first surface of the support member and having a redistribution layer, the primer layer being disposed between the connection member and the support member; a semiconductor chip having an active surface on which connection pads are disposed and an inactive surface opposing the active surface, the connection pads being electrically connected to the redistribution layer; and an encapsulant covering the second surface of the support member and the inactive surface of the semiconductor chip.

Abstract: Disclosed is a battery cell assembly with improved cooling efficiency. The battery cell assembly includes a cooling fin having a tube through which a coolant flows; at least one frame member; at least one battery cell disposed to face the cooling fin; a first cooling port welded to an inlet formed at one end of the tube of the cooling fin; and a second cooling port welded to an outlet formed at the other end of the tube of the cooling fin. The first cooling port and the second cooling port are made of the same material as the tube.

Abstract: A battery module and a battery pack are disclosed. The battery module includes a module frame having a top plate and a bottom plate vertically spaced apart from each other at a predetermined interval and disposed to face each other, and at least one barrier configured to vertically partition a space between the top and bottom plates; two or more battery submodules arranged inside the module frame in a matrix form with the at least one barrier being interposed therebetween; and a left side plate and a right side plate configured to cover a left side and a right side of the module frame and a front cover and a rear cover configured to cover a front side and a rear side of the module frame.

Abstract: Provided is an apparatus for generating an identification key by a probabilistic determination of a short occurring between nodes constituting a circuit, by violating a design rule provided during a semiconductor manufacturing process. The identification key generating apparatus may include an identification key generator to generate an identification key based on whether a contact or a via used to electrically connect conductive layers in a semiconductor chip shorts the conductive layers, and an identification key reader to read the identification key by reading whether the contact or the via shorts the conductive layers.

Abstract: A bio signal measuring apparatus is provided which a receiver configured to receive a pulse signal penetrating a person to be measured, a processing unit configured to process the pulse signal to analyze a bandwidth of the pulse signal and to measure a bio signal of the person to be measured based on an analysis result on the bandwidth, and a storage unit configured to store data used to measure the bio signal.

Abstract: A fan-out semiconductor package includes: a core member including a support layer, a first wiring layer, a second wiring layer, and through-vias and having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant covering the core member and the semiconductor chip and filling at least portions of the through-hole; a connection member including an insulating layer disposed on the first wiring layer and the semiconductor chip, a redistribution layer disposed on the insulating layer, first vias electrically connecting the redistribution layer and the connection pads to each other, and second vias electrically connecting the redistribution layer and the first wiring layer to each other; and a passivation layer disposed on the insulating layer and covering the redistribution layer, wherein a thickness of the passivation layer is within half a distance from an inactive surface of the semiconductor chip to a lower surface of the encapsulant.

Abstract: Provided is an apparatus for generating an identification key by a probabilistic determination of a short occurring between nodes constituting a circuit, by violating a design rule provided during a semiconductor manufacturing process. The identification key generating apparatus may include an identification key generator to generate an identification key based on whether a contact or a via used to electrically connect conductive layers in a semiconductor chip shorts the conductive layers, and an identification key reader to read the identification key by reading whether the contact or the via shorts the conductive layers.

Abstract: A fiber-type electronic device comprising a pattern for electronic devices stacked on a fiber filament substrate is provided. It is possible to manufacture an electronic device directly on a fiber filament substrate by applying the pattern for electronic devices. Thus, it can be widely used for wearable devices and the like. The pattern for electronic devices is manufactured by a method for forming a pattern for electronic devices comprising an exposure process using a maskless exposure apparatus. Thus, it is possible to manufacture a pattern for electronic devices on a fiber filament substrate through a continuous process and thus to increase the process efficiency.

Abstract: Provided are a composite liquid pharmaceutical composition and a preparation method thereof, wherein the composite liquid pharmaceutical composition includes a Hedera helix leaf extract and a dry powder of a mixture including a Pelargonium sidoides extract and maltodextrin.

Abstract: Disclosed is a method of playing a virtual reality image, and the method includes receiving, by a client, an image frame from a server, allocating the received image frame to a first layer, generating a second layer including at least one graphic user interface, composing the first layer and the second layer to generate a final image frame, and displaying the generated final image frame.