Abstract: A memory controller includes a ring oscillator to generate and to output at least one oscillation clock, an oscillation counter to count the output oscillation clocks, a sampler to receive the reference clock so as to sample a number of the counted oscillation clocks during a period of the reference clock, and a phase value output unit to output the sampled number of oscillation clocks as a phase value of the reference clock. Thereby, the memory controller can detect the phase value using only two periods of the reference clock, and reduce the initial operation time of a system.

Abstract: A data control circuit for a double data rate (DDR) synchronous dynamic random-access memory (SDRAM) that secures a stable reading/writing operation of DDR SDRAM data by generating an actively controllable internal data strobe signal. The data control circuit includes an internal data strobe signal generating circuit generating and outputting an internal data strobe signal a rising edge of which is located in a center part of valid DDR SDRAM data; a read data control circuit for receiving the internal data strobe signal, generated from the internal data strobe signal generating circuit as a clock input, dividing captured data into even data and odd data, and transmitting the even data and the odd data to a system bus; and a write data control circuit transmitting the internal data strobe signal input from the internal data strobe signal generating circuit to a DDR SDRAM device as a data strobe signal.