Abstract: An encoding/decoding apparatus and method for controlling a channel signal is disclosed, wherein the encoding apparatus may include an encoder to encode an object signal, a channel signal, and rendering information for the channel signal, and a bit stream generator to generate, as a bit stream, the encoded object signal, the encoded channel signal, and the encoded rendering information for the channel signal.

Abstract: Disclosed is a surgical linear stapler comprising: a staple cartridge which is internally loaded with staples for stapling a surgical site; a cartridge accommodating channel which is formed with a cartridge accommodating groove to accommodate the staple cartridge therein; an anvil which corresponds to the staple cartridge and shapes the staple discharged from the staple cartridge; and a cutter which moves along a lengthwise direction of the staple cartridge by external force and cuts a surgical site arranged in between the staple cartridge and the anvil, in which distances from the cutting section of the surgical site to opposite stapling lines are different from each other, thereby stably and conveniently obtaining tissue for pathological examination, which is not damaged by a staple.

Abstract: Disclosed is an end effector of a surgical linear stapler, which includes a staple cartridge, an anvil, a pusher unit, a driving wedge, a stabilizer unit and a blade unit, wherein the stabilizer unit is arranged on the staple cartridge while neighboring on the pusher unit and at least partially discharged from the staple cartridge by the driving wedge so as to hold tissue placed in between the staple cartridge and the anvil.

Abstract: Disclosed is an end effector of a surgical linear stapler, which includes a staple cartridge, an anvil, a pusher unit, a driving wedge, a stabilizer unit and a blade unit, wherein the stabilizer unit is arranged on the staple cartridge while neighboring on the pusher unit and at least partially discharged from the staple cartridge by the driving wedge so as to hold tissue placed in between the staple cartridge and the anvil.

Abstract: Provided are a method of fabricating an improved multi-gate transistor and a multi-gate transistor fabricated using the method, in which an active pattern is formed on a substrate, the active pattern having two or more surfaces on which channel regions are to be formed, a gate insulating layer is formed on the channel regions, and a patterned gate electrode is formed on the gate insulating layer while maintaining a shape conformal to the active pattern.

Abstract: A transistor for a semiconductor device may include a lower semiconductor layer, an active pattern, including a groove region, on the lower semiconductor layer, a gate pattern at least partially overlapping the active pattern including the groove region, and a gate insulating layer interposed between the active pattern and the gate pattern, wherein a bottom surface of the groove region may be lower than a top surface of the active pattern and higher than a lower surface of the active pattern.

Abstract: In a transistor and a method of manufacturing the transistor, the transistor includes a dummy structure enclosing source/drain structures and channel structures. Thus, a gate electrode of the transistor may be efficiently formed over the channel structures. In addition, the source/drain structure may not grow exceedingly in an epitaxial growth process employed for forming the source/drain structure.

Abstract: In an asymmetrical SRAM device, and a method of manufacturing the same, the asymmetrical SRAM device includes a semiconductor substrate on which a plurality of unit cell regions are defined, and a plurality of active regions formed in each of the unit cell regions of the semiconductor substrate, wherein the active regions of each unit cell region are a mirror image of active regions of an adjacent one of the plurality of unit cell regions with respect to a boundary line between the adjacent unit cell regions.

Abstract: Provided are a method of fabricating an improved multi-gate transistor and a multi-gate transistor fabricated using the method, in which an active pattern is formed on a substrate, the active pattern having two or more surfaces on which channel regions are to be formed, a gate insulating layer is formed on the channel regions, and a patterned gate electrode is formed on the gate insulating layer while maintaining a shape conformal to the active pattern.

Abstract: In a method of forming a semiconductor device, a copper diffusion-prevention layer is formed underneath a substrate. Impurity regions are formed on the surface of the substrate. A copper wiring is electrically connected to the impurity regions. The copper diffusion-prevention layer is formed before forming the lightly doped source/drain regions to prevent copper atoms from diffusing into the substrate.

Abstract: Example embodiments relate to a semiconductor device and a method of fabricating the same. A dummy pattern may be formed on a semiconductor substrate. Source and drain regions may be formed on the semiconductor substrate at sides of the dummy pattern. A first metal silicide layer may be formed on the source and drain regions. A recess region may be formed in the semiconductor substrate under the dummy pattern. A gate insulating layer and a gate electrode may be formed in the recess region.

Abstract: A transistor for a semiconductor device may include a lower semiconductor layer, an active pattern, including a groove region, on the lower semiconductor layer, a gate pattern at least partially overlapping the active pattern including the groove region, and a gate insulating layer interposed between the active pattern and the gate pattern, wherein a bottom surface of the groove region may be lower than a top surface of the active pattern and higher than a lower surface of the active pattern.

Abstract: In a transistor and a method of manufacturing the transistor, the transistor includes a dummy structure enclosing source/drain structures and channel structures. Thus, a gate electrode of the transistor may be efficiently formed over the channel structures. In addition, the source/drain structure may not grow exceedingly in an epitaxial growth process employed for forming the source/drain structure.

Abstract: Disclosed is to a single electron device, a method of manufacturing the same, and a method of simultaneously manufacturing a single electron device and an MOS transistor. Accordingly, the single electron device of the present invention comprises, on a substrate, semiconductor layers in which a source region and a drain region spaced a predetermined distance apart are formed, hemisphere-type silicon layer formed between the semiconductor layers as an active layer, the hemisphere-type silicon layer having a plurality of electron islands, a gate insulating layer formed on a top surface of the entire structure, and a gate electrode formed on the gate insulating layer in order to apply voltage to the active layer.

Abstract: Provided are a method of fabricating an improved multi-gate transistor and a multi-gate transistor fabricated using the method, which can reproduce a profile of a gate electrode in a stable manner. The method includes forming an active pattern on a substrate, the active pattern having two or more surfaces on which channel regions are to be formed, forming a gate insulating layer on the channel regions, and forming a patterned gate electrode on the gate insulating layer while maintaining a shape conformal to the active pattern.

Abstract: In an asymmetrical SRAM device, and a method of manufacturing the same, the asymmetrical SRAM device includes a semiconductor substrate on which a plurality of unit cell regions are defined, and a plurality of active regions formed in each of the unit cell regions of the semiconductor substrate, wherein the active regions of each unit cell region are a mirror image of active regions of an adjacent one of the plurality of unit cell regions with respect to a boundary line between the adjacent unit cell regions.

Abstract: In a method of forming a gate of a semiconductor device, a gate insulating layer and a polysilicon layer are successively formed on a substrate that is partitioned into a field region and an active region. A hard mask is formed on the polysilicon layer. The hard mask overlaps with the active region and has a spacer pattern that partially extends into the field region. The polysilicon layer is partially etched using the hard mask as an etching mask to form the gate. The gate overlaps with the active region and has an end portion positioned in the field region. The end portion has a width at least as large as a thickness of the spacer pattern.

Abstract: In a method of forming a semiconductor device, a copper diffusion-prevention layer is formed underneath a substrate. Impurity regions are formed on the surface of the substrate. A copper wiring is electrically connected to the impurity regions. The copper diffusion-prevention layer is formed before forming the lightly doped source/drain regions to prevent copper atoms from diffusing into the substrate.

Abstract: Disclosed is to a single electron device, a method of manufacturing the same, and a method of simultaneously manufacturing a single electron device and an MOS transistor. Accordingly, the single electron device of the present invention comprises, on a substrate, semiconductor layers in which a source region and a drain region spaced a predetermined distance apart are formed, hemisphere-type silicon layer formed between the semiconductor layers as an active layer, the hemisphere-type silicon layer having a plurality of electron islands, a gate insulating layer formed on a top surface of the entire structure, and a gate electrode formed on the gate insulating layer in order to apply voltage to the active layer.

Abstract: The method for forming a capacitor of a semiconductor device includes the steps of forming a first insulation layer on the upper surface of a semiconductor substrate, forming a second insulation layer on the upper surface of the first insulation layer, and forming a third insulation layer on the upper surface of the second insulation layer. The third insulation layer and the second insulation layer are sequentially etched to form at least one hole over a cell region of the semiconductor substrate. Next a conductive layer is formed over the semiconductor substrate, and Chemical Mechanical Polishing (CMP) is performed until an upper surface of the third insulation layer is exposed. Then, portions of the third insulation layer and slurry material from the CMP are removed from the cell region.