Abstract: Semiconductor wafers utilize asymmetric edge profiles (EP) to facilitate higher yield semiconductor device processing. These edge profiles are configured to reduce the volume of thin film residues that may form on a top surface of a semiconductor wafer at locations adjacent a peripheral edge thereof. These edges profiles are also configured to inhibit redeposition of residue particulates on the top surfaces of the wafers during semiconductor processing steps. Such steps may include surface cleaning and rinsing steps that may include passing a cleaning or rinsing solution across a wafer or batch of wafers that are held by a cartridge and submerged in the solution.

Abstract: An apparatus for analyzing a substrate employing a copper decoration includes a bath having at least two receiving containers for receiving electrolytes, slots formed at insides of the receiving containers for receiving substrates to be analyzed in a direction that is normal to a bottom face of the bath, lower copper plates provided in the receiving containers, the lower copper plates making contact with entire rear faces of the substrates received in the receiving containers, upper copper plates provided in the receiving containers, each of the upper copper plates corresponding to a respective one of the lower copper plates, and separated from front faces of the substrates, and a power source connected to the upper copper plates and the lower copper plates for providing voltages to the same. A plurality of substrates may be simultaneously analyzed using one apparatus thereby greatly reducing an amount of time required for the analysis.

Abstract: A susceptor for use in a deposition apparatus includes a recess in which a wafer is received, and a stress-reducing bumper disposed along the side of the recess. The stress-reducing bumper is of material having ductility at a relatively high temperature. Therefore, when the wafer contacts the stress-reducing bumper, such as may occur due to thermal expansion of the wafer during processing, the force of the impact on the wafer is minimized by an elastic deformation of the stress-reducing bumper. As a result, defects, such as slip dislocations at the outer peripheral edge of the wafer, are prevented.

Abstract: An apparatus for analyzing a substrate employing a copper decoration includes a bath having at least two receiving containers for receiving electrolytes, slots formed at insides of the receiving containers for receiving substrates to be analyzed in a direction that is normal to a bottom face of the bath, lower copper plates provided in the receiving containers, the lower copper plates making contact with entire rear faces of the substrates received in the receiving containers, upper copper plates provided in the receiving containers, each of the upper copper plates corresponding to a respective one of the lower copper plates, and separated from front faces of the substrates, and a power source connected to the upper copper plates and the lower copper plates for providing voltages to the same. A plurality of substrates may be simultaneously analyzed using one apparatus thereby greatly reducing an amount of time required for the analysis.

Abstract: Types of defects on a wafer are discriminated according to defect measurements obtained from a wafer inspection system which includes a plurality of dark field detectors. Using the wafer measurement system, it is determined whether first, second and third conditions are satisfied. The first condition is when a size of a defect on the wafer measured by the wafer inspection system is smaller than a limit value denoting a maximum size of crystal originated particles. The second condition is when a correlation between a plurality of defect light intensity values detected by a plurality of dark field detectors of the wafer measurement system satisfies a reference value. The third condition is when a location of the defect measured by the wafer inspection system is within a vacancy-rich area of the wafer. The type of the defect is then determined to be a crystal originated particle when the first, second and third conditions are all satisfied.

Abstract: Semiconductor wafers utilize asymmetric edge profiles (EP) to facilitate higher yield semiconductor device processing. These edge profiles are configured to reduce the volume of thin film residues that may form on a top surface of a semiconductor wafer at locations adjacent a peripheral edge thereof. These edges profiles are also configured to inhibit redeposition of residue particulates on the top surfaces of the wafers during semiconductor processing steps. Such steps may include surface cleaning and rinsing steps that may include passing a cleaning or rinsing solution across a wafer or batch of wafers that are held by a cartridge and submerged in the solution.

Abstract: Embodiments of the present invention provide methods for measuring a wafer surface. A portion of the wafer surface is measured using a particle counter to provide first measurements corresponding to a plurality of points on the wafer surface. A selected area of the wafer surface including one of the plurality of points is measured using an atomic force microscope (AFM) to provide a microroughness measurement of the selected area. The selected area is a localized area of the portion of the wafer surface measured using the particle counter. The first measurements and the microroughness measurement are provided as a measurement of the wafer surface. The portion measured using a particle counter may, for example, be substantially the entire wafer surface.

Abstract: A method of analyzing the morphology of bulk and surface defects on a semiconductor wafer includes: determining a location of the defects; marking an indication proximate the location; milling the wafer using the indication, to thereby make a specimen; and analyzing the specimen to obtain the defects' morphology. Bulk defects as deep 5-250 &mgr;m can be detected and surface defects as deep as 10 &mgr;m from the wafer's surface can be detected. Both morphology analyses preferably include using TEM (Transmission Electron Microscopy). The location determination for both defects preferably includes projecting a laser beam onto the wafer. By obtaining the morphology of the defects, the cause of failure due to the bulk defects and surface defects can accurately be investigated, increasing semiconductor devices' reliability.

Abstract: Compositions useful for polishing wafers to be used in microelectronic devices comprise silicon dioxide, aluminum oxide, sodium hydroxide, and water. Cleaning compositions for removing electron wax from wafers to be used in microelectronic devices comprise from about 2 to about 6 percent by weight of ammonium hydroxide, from about 10 to about 22 percent by weight of hydrogen peroxide, and water.