Patents by Inventor Tae-Yeol Kim

Tae-Yeol Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10847464
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device including an insulating structure having an opening; a conductive pattern disposed in the opening; a barrier structure covering a bottom surface of the conductive pattern, the barrier structure extending between the conductive pattern and side walls of the opening; and a nucleation structure disposed between the conductive pattern and the barrier structure. The nucleation structure includes a first nucleation layer that contacts the barrier structure, and a second nucleation layer that contacts the conductive pattern, and a top end portion of the second nucleation layer is higher than a top end portion of the first nucleation layer.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: November 24, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae Yeol Kim, Ji Won Kang, Chung Hwan Shin, Jin Il Lee, Sang Jin Hyun
  • Publication number: 20200152577
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device including an insulating structure having an opening; a conductive pattern disposed in the opening; a barrier structure covering a bottom surface of the conductive pattern, the barrier structure extending between the conductive pattern and side walls of the opening; and a nucleation structure disposed between the conductive pattern and the barrier structure. The nucleation structure includes a first nucleation layer that contacts the barrier structure, and a second nucleation layer that contacts the conductive pattern, and a top end portion of the second nucleation layer is higher than a top end portion of the first nucleation layer.
    Type: Application
    Filed: January 9, 2020
    Publication date: May 14, 2020
    Inventors: TAE YEOL KIM, JI WON KANG, CHUNG HWAN SHIN, JIN IL LEE, SANG JIN HYUN
  • Patent number: 10580736
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device including an insulating structure having an opening; a conductive pattern disposed in the opening; a barrier structure covering a bottom surface of the conductive pattern, the barrier structure extending between the conductive pattern and side walls of the opening; and a nucleation structure disposed between the conductive pattern and the barrier structure. The nucleation structure includes a first nucleation layer that contacts the barrier structure, and a second nucleation layer that contacts the conductive pattern, and a top end portion of the second nucleation layer is higher than a top end portion of the first nucleation layer.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: March 3, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae Yeol Kim, Ji Won Kang, Chung Hwan Shin, Jin Il Lee, Sang Jin Hyun
  • Publication number: 20190295958
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device including an insulating structure having an opening; a conductive pattern disposed in the opening; a barrier structure covering a bottom surface of the conductive pattern, the barrier structure extending between the conductive pattern and side walls of the opening; and a nucleation structure disposed between the conductive pattern and the barrier structure. The nucleation structure includes a first nucleation layer that contacts the barrier structure, and a second nucleation layer that contacts the conductive pattern, and a top end portion of the second nucleation layer is higher than a top end portion of the first nucleation layer.
    Type: Application
    Filed: June 14, 2019
    Publication date: September 26, 2019
    Inventors: TAE YEOL KIM, JI WON KANG, CHUNG HWAN SHIN, JIN IL LEE, SANG JIN HYUN
  • Patent number: 10366955
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device including an insulating structure having an opening; a conductive pattern disposed in the opening; a barrier structure covering a bottom surface of the conductive pattern, the barrier structure extending between the conductive pattern and side walls of the opening; and a nucleation structure disposed between the conductive pattern and the barrier structure. The nucleation structure includes a first nucleation layer that contacts the barrier structure, and a second nucleation layer that contacts the conductive pattern, and a top end portion of the second nucleation layer is higher than a top end portion of the first nucleation layer.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: July 30, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae Yeol Kim, Ji Won Kang, Chung Hwan Shin, Jin Il Lee, Sang Jin Hyun
  • Publication number: 20180374915
    Abstract: A semiconductor device is provided including a resistor structure, the semiconductor device including a substrate having an upper surface perpendicular to a first direction; a resistor structure including a first insulating layer on the substrate, a resistor layer on the first insulating layer, and a second insulating layer on the resistor layer; and a resistor contact penetrating the second insulating layer and the resistor layer. The tilt angle of a side wall of the resistor contact with respect to the first direction varies according to a height from the substrate. The semiconductor device has a low contact resistance and a narrow variation of contact resistance.
    Type: Application
    Filed: January 5, 2018
    Publication date: December 27, 2018
    Inventors: Tae-yeol KIM, Hyon-wook RA, Seo-bum LEE, Jun-soo KIM, Chung-hwan SHIN
  • Publication number: 20180211922
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device including an insulating structure having an opening; a conductive pattern disposed in the opening; a barrier structure covering a bottom surface of the conductive pattern, the barrier structure extending between the conductive pattern and side walls of the opening; and a nucleation structure disposed between the conductive pattern and the barrier structure. The nucleation structure includes a first nucleation layer that contacts the barrier structure, and a second nucleation layer that contacts the conductive pattern, and a top end portion of the second nucleation layer is higher than a top end portion of the first nucleation layer.
    Type: Application
    Filed: November 8, 2017
    Publication date: July 26, 2018
    Inventors: TAE YEOL KIM, JI WON KANG, CHUNG HWAN SHIN, JIN IL LEE, SANG JIN HYUN
  • Patent number: 8530349
    Abstract: Provided are semiconductor devices and methods for fabricating the same. A method for fabricating a semiconductor device includes: forming an interlayer dielectric layer including an opening in which a lower conductive layer is exposed; forming a barrier layer on the interlayer dielectric layer and on the lower conductive layer the opening; forming an anti-seed generation region on a surface of the barrier layer which is provided on a top surface of the interlayer dielectric layer and an upper sidewall of the opening; and filling the opening with conductive material to form a conductive layer.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: September 10, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jinwoo Choi, Geun Hee Jeong, Tae-Yeol Kim
  • Publication number: 20110256717
    Abstract: Provided are semiconductor devices and methods for fabricating the same. A method for fabricating a semiconductor device includes: forming an interlayer dielectric layer including an opening in which a lower conductive layer is exposed; forming a barrier layer on the interlayer dielectric layer and on the lower conductive layer the opening; forming an anti-seed generation region on a surface of the barrier layer which is provided on a top surface of the interlayer dielectric layer and an upper sidewall of the opening; and filling the opening with conductive material to form a conductive layer.
    Type: Application
    Filed: March 31, 2011
    Publication date: October 20, 2011
    Inventors: Jinwoo CHOI, Geun Hee Jeong, Tae-Yeol Kim