Abstract: An image sensor chip includes a first wafer and a second wafer. The first wafer includes an image sensor having a plurality of sub-pixels, each of which is configured to detect at least one photon and output a sub-pixel signal according to a result of the detection. The image processor is configured to process sub-pixel signals for each sub-pixel and generate image data. The first wafer and the second wafer are formed in a wafer stack structure.

Abstract: An image sensor is provided. The image sensor includes a well of a second conductivity type formed on an impurity layer of a first conductivity type, source and drain regions of the first conductivity type, formed in the well to be spaced apart from each other, a first photo diode of the first conductivity type formed in the well to overlap the source and drain regions, a second photo diode of the first conductivity type formed so as not to overlap the source and drain regions and formed to be adjacent to the first photo diode, and a gate electrode formed on the first and second photo diodes.

Abstract: ACMOS image sensor includes a pixel array having a plurality of pixels. Each of the plurality of pixels includes: a photogate structure configured to be controlled based on a first gate voltage; and a sensing transistor including a charge pocket region formed in a substrate region, the sensing transistor being configured to be controlled based on a second gate voltage. Based on the first gate voltage, the photogate structure is configured to integrate charges generated in response to light incident on the substrate region. The sensing transistor is configured to adjust at least one of a threshold voltage of the sensing transistor and a current flow in the sensing transistor according to charges transferred from the photogate structure to the charge pocket region based on a difference between the first gate voltage and the second gate voltage.

Abstract: A sub pixel includes a photodetector and a column line output circuit. The photodetector is configured to output an electrical signal based on a detected amount of photons. The column line output circuit is configured to generate an output signal based on the electrical signal. The output signal is one of a current from a current source and a comparison signal indicative of binary output data.

Abstract: A unit pixel of a three-dimensional image sensor includes a non-silicon photodetector and at least one readout circuit. The non-silicon photodetector is formed at a silicon substrate, and the non-silicon photodetector comprising at least one of non-silicon materials to generate a photocharge in response to incident light. The at least one readout circuit is formed at the silicon substrate, the at least one readout circuit outputs a sensing signal based on the photocharge, and the sensing signal generates depth information on a distance to an object.

Abstract: In a method of operating an image sensor, a noise voltage of a floating diffusion region is sampled after a reset voltage is applied to the floating diffusion region. A storage region, in which a photo-charge is stored, is electrically connected to the floating diffusion region after sampling the noise voltage, and a demodulation voltage of the floating diffusion region is sampled after the storage region and the floating diffusion region are electrically-connected. A voltage is determined based on the noise voltage and the demodulation voltage.

Abstract: A PRAM device includes a lower electrode, a phase-change nanowire and an upper electrode. The phase-change nanowire may be electrically connected to the lower electrode and includes a single element. The upper electrode may be electrically connected to the phase-change nanowires.

Abstract: A three-dimensional image sensor may include a light source module configured to emit at least one light to an object, a sensing circuit configured to polarize a received light that represents the at least one light reflected from the object and configured to convert the polarized light to electrical signals, and a control unit configured to control the light source module and sensing circuit. A camera may include a receiving lens; a sensor module configured to generate depth data, the depth data including depth information of objects based on a received light from the objects; an engine unit configured to generate a depth map of the objects based on the depth data, configured to segment the objects in the depth map, and configured to generate a control signal for controlling the receiving lens based on the segmented objects; and a motor unit configured to control focusing of the receiving lens.

Abstract: A PRAM device includes a lower electrode, a phase-change nanowire and an upper electrode. The phase-change nanowire may be electrically connected to the lower electrode and includes a single element. The upper electrode may be electrically connected to the phase-change nanowires.

Abstract: A PRAM device includes a lower electrode, a phase-change nanowire and an upper electrode. The phase-change nanowire may be electrically connected to the lower electrode and includes a single element. The upper electrode may be electrically connected to the phase-change nanowires.

Abstract: A thermal image sensor including a chalcogenide material, and a method of fabricating the thermal image sensor are provided. The thermal image sensor includes a first metal layer formed on a substrate; a cavity exiting the first metal layer adapted for absorbing infrared rays; a bolometer resistor formed on the cavity and including a chalcogenide material; and a second metal layer formed on the bolometer resistor. The thermal image sensor includes a first metal layer formed on a substrate; an insulating layer formed on the first metal layer; a bolometer resistor formed on the insulating layer, including a chalcogenide material and having a thickness corresponding to ¼ of an infrared wavelength (?); the thermal image sensor further includes a second metal layer formed on the bolometer resistor.

Abstract: A multi-level phase change random access memory device includes a first electrode, a second electrode, and a phase change material disposed between the first electrode and the second electrode. The multi-level phase change random access memory device also includes a variable bias source coupled to the first electrode. The variable bias source provides a respective bias applied at the first electrode to form a portion of the phase change material to have one of an amorphous state and different crystal states for storing multi-bits data.

Abstract: A phase change material layer includes antimony (Sb) and at least one of indium (In) and gallium (Ga). A phase change memory device includes a storage node including a phase change material layer and a switching device connected to the storage node. The phase change material layer includes Sb and at least one of In and Ga.

Abstract: A photodiode includes a p-type semiconductor material and an n-type chalcogenide compound. The p-type semiconductor material and the n-type chalcogenide compound form a pn-junction.

Abstract: Provided is a phase-change random access memory (PRAM). The PRAM includes a bottom electrode, a bottom electrode contact layer, which is formed on one area of the bottom electrode, and an insulating layer, which is formed on a side of the bottom electrode contact layer, a phase-change layer, which is formed on the bottom electrode contact layer and the insulating layer and is formed of a phase-change material having a crystallization temperature between 100° C. and 150° C., and a top electrode, which is formed on the phase-change layer.

Abstract: Disclosed may be a phase change material alloy, a phase change memory device including the same, and methods of manufacturing and operating the phase change memory device. The phase change material alloy may include Si and Sb. The alloy may be a Si—O—Sb alloy further including O. The Si—O—Sb alloy may be SixOySbz, wherein, when x/(x+z) may be x1, 0.05?x1?0.30, 0.00?y?0.50, and x+y+z may be 1. The Si—O—Sb alloy may further comprise an element other than Si, O, and Sb.

Abstract: A method includes providing packets to demodulate a modulated photon signal output from a light source, wherein each packet includes a first interval and a second interval, and providing oscillation signals respectively having different phases from one another to photogates during the first interval of each of the packets. The light source is disabled and a direct current (DC) voltage is provided to the photogates during the second interval of each of the packets.

Abstract: A PRAM device includes a lower electrode, a phase-change nanowire and an upper electrode. The phase-change nanowire may be electrically connected to the lower electrode and includes a single element. The upper electrode may be electrically connected to the phase-change nanowires.

Abstract: Provided is a phase-change memory using a single-element semimetallic thin film. The device includes a storage node having a phase-change material layer and a switching element connected to the storage node, wherein the storage node includes a single-element semimetallic thin film which is formed between an upper electrode and a lower electrode. Thus, the write speed of the phase-change memory can be increased compared with the case of a Ge—Sb—Te (GST) based material.

Abstract: A multi-level phase change random access memory device includes a first electrode, a second electrode, and a phase change material disposed between the first electrode and the second electrode. The multi-level phase change random access memory device also includes a variable bias source coupled to the first electrode. The variable bias source provides a respective bias applied at the first electrode to form a portion of the phase change material to have one of an amorphous state and different crystal states for storing multi-bits data.