Patents by Inventor Tae Yong Bae

Tae Yong Bae has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11915998
    Abstract: In one example, a semiconductor device comprises a substrate having a top surface and a bottom surface, an electronic device on the bottom surface of the substrate, a leadframe on the bottom surface of the substrate, the leadframe comprising a paddle, wherein the paddle is coupled to the electronic device, and a lead electrically coupled to the electronic device. The semiconductor device further comprises a first protective material contacting the bottom surface of the substrate and a side surface of the electronic device.
    Type: Grant
    Filed: August 12, 2022
    Date of Patent: February 27, 2024
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Hyung Jun Cho, Kyoung Yeon Lee, Tae Yong Lee, Jae Min Bae
  • Patent number: 11876017
    Abstract: Integrated circuit devices and methods of forming the same are provided. The methods of forming an integrated circuit device may include forming a first insulating layer and a via contact on a substrate. The substrate may include an upper surface facing the via contact, and the via contact may be in the first insulating layer and may include a lower surface facing the substrate and an upper surface opposite to the lower surface. The methods may also include forming a second insulating layer and a metallic wire on the via contact. The metallic wire may be in the second insulating layer and may include a lower surface that faces the substrate and contacts the upper surface of the via contact. Both the lower surface of the metallic wire and an interface between the metallic wire and the via contact may have a first width in a horizontal direction that is parallel to the upper surface of the substrate.
    Type: Grant
    Filed: December 15, 2021
    Date of Patent: January 16, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae Yong Bae, Hoon Seok Seo, Ki Hyun Park, Hak-Sun Lee
  • Publication number: 20220108920
    Abstract: Integrated circuit devices and methods of forming the same are provided. The methods of forming an integrated circuit device may include forming a first insulating layer and a via contact on a substrate. The substrate may include an upper surface facing the via contact, and the via contact may be in the first insulating layer and may include a lower surface facing the substrate and an upper surface opposite to the lower surface. The methods may also include forming a second insulating layer and a metallic wire on the via contact. The metallic wire may be in the second insulating layer and may include a lower surface that faces the substrate and contacts the upper surface of the via contact. Both the lower surface of the metallic wire and an interface between the metallic wire and the via contact may have a first width in a horizontal direction that is parallel to the upper surface of the substrate.
    Type: Application
    Filed: December 15, 2021
    Publication date: April 7, 2022
    Inventors: Tae Yong Bae, Hoon Seok Seo, Ki Hyun Park, Hak-Sun Lee
  • Patent number: 11232986
    Abstract: Integrated circuit devices and methods of forming the same are provided. The methods of forming an integrated circuit device may include forming a first insulating layer and a via contact on a substrate. The substrate may include an upper surface facing the via contact, and the via contact may be in the first insulating layer and may include a lower surface facing the substrate and an upper surface opposite to the lower surface. The methods may also include forming a second insulating layer and a metallic wire on the via contact. The metallic wire may be in the second insulating layer and may include a lower surface that faces the substrate and contacts the upper surface of the via contact. Both the lower surface of the metallic wire and an interface between the metallic wire and the via contact may have a first width in a horizontal direction that is parallel to the upper surface of the substrate.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: January 25, 2022
    Inventors: Tae Yong Bae, Hoon Seok Seo, Ki Hyun Park, Hak-Sun Lee
  • Patent number: 11075160
    Abstract: A semiconductor device is provided. The semiconductor device includes a first wiring and a second wiring disposed at a first metal level, a third wiring and a fourth wiring disposed at a second metal level different from the first metal level, a first via which directly connects the first wiring and the third wiring, a fifth wiring disposed at a third metal level between the first metal level and the second metal level and connected to the second wiring, and a second via which directly connects the fourth wiring and the fifth wiring.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: July 27, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Doo-Hwan Park, Seong Ho Park, Kyoung Pil Park, Tae Yong Bae, Eun-Chul Seo
  • Publication number: 20210111070
    Abstract: Integrated circuit devices and methods of forming the same are provided. The methods of forming an integrated circuit device may include forming a first insulating layer and a via contact on a substrate. The substrate may include an upper surface facing the via contact, and the via contact may be in the first insulating layer and may include a lower surface facing the substrate and an upper surface opposite to the lower surface. The methods may also include forming a second insulating layer and a metallic wire on the via contact. The metallic wire may be in the second insulating layer and may include a lower surface that faces the substrate and contacts the upper surface of the via contact. Both the lower surface of the metallic wire and an interface between the metallic wire and the via contact may have a first width in a horizontal direction that is parallel to the upper surface of the substrate.
    Type: Application
    Filed: February 10, 2020
    Publication date: April 15, 2021
    Inventors: Tae Yong BAE, Hoon Seok SEO, Ki Hyun PARK, Hak-Sun LEE
  • Publication number: 20200013715
    Abstract: A semiconductor device is provided. The semiconductor device includes a first wiring and a second wiring disposed at a first metal level, a third wiring and a fourth wiring disposed at a second metal level different from the first metal level, a first via which directly connects the first wiring and the third wiring, a fifth wiring disposed at a third metal level between the first metal level and the second metal level and connected to the second wiring, and a second via which directly connects the fourth wiring and the fifth wiring.
    Type: Application
    Filed: April 16, 2019
    Publication date: January 9, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Doo-Hwan Park, Seong Ho Park, Kyoung Pil Park, Tae Yong Bae, Eun-Chul Seo