Patents by Inventor Tae Yong Kwon

Tae Yong Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10566245
    Abstract: A method of fabricating a gate all around semiconductor device is provided.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: February 18, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae Yong Kwon, Oh Seong Kwon
  • Patent number: 10559644
    Abstract: A display device includes a substrate having a pixel area with at least a first rounded corner portion and first to third non-pixel areas arranged sequentially along an outer circumference of the pixel area. An internal circuit in the first non-pixel area has a first end portion adjacent to the first rounded corner portion of the pixel area. The first end portion of the internal circuit is rounded in accordance with the first rounded corner portion. A plurality of routing wires are in the third non-pixel area below the pixel area. The routing wires extending to the pixel area via the second non-pixel area and the first non-pixel area. The routing wires include at least a first routing wire connected to the pixel area passing an area of the first end portion of the internal circuit.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: February 11, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Seung Kyu Lee, Yang Wan Kim, Sun Ja Kwon, Byung Sun Kim, Hyun Ae Park, Su Jin Lee, Jae Yong Lee, Tae Hoon Kwon, Seung Ji Cha
  • Publication number: 20190386136
    Abstract: Vertical field-effect transistor (VFET) devices and methods of forming VFET devices are provided. The methods may include forming a channel region that protrudes from an upper surface of a substrate in a vertical direction, forming a gate insulator layer on a side of the channel region, after forming the gate insulator layer, forming a top source/drain on the channel region, and forming a gate electrode on the gate insulator layer.
    Type: Application
    Filed: February 26, 2019
    Publication date: December 19, 2019
    Inventors: Tae Yong KWON, Kang Ill Seo, Oh Seong Kwon, Ki Sik Choi
  • Patent number: 10510822
    Abstract: A display device includes a substrate having a display area and a non-display area, a plurality of pixels in the display area, scan lines for supplying a scan signal to the pixels, the scan lines extending in a first direction, data lines for supplying a data signal to the pixels, the data lines extending in a second direction crossing the first direction, and a first dummy part in the non-display area, adjacent to an outermost pixel, connected to an outermost data line of the display area, forming a parasitic capacitor with the outermost pixel, and including a first dummy data line and a first dummy power pattern extending in parallel to the data lines.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: December 17, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yang Wan Kim, Ji Hyun Ka, Tae Hoon Kwon, Byung Sun Kim, Hyung Jun Park, Su Jin Lee, Jae Yong Lee, Jin Tae Jeong, Seung Ji Cha
  • Patent number: 10508997
    Abstract: A method of analyzing fines migration in a multiphase flow in a sediment layer using X-ray computed tomography (CT) image includes, preparing an X-ray CT image analysis sample; analyzing an X-ray CT image during a depressurization process; calibrating and calculating a fines content; and estimating a fines migration analysis result.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: December 17, 2019
    Assignee: Korea Institute of Geoscience and Mineral Resources
    Inventors: Joo-Yong Lee, Min-Hui Lee, Gyeol Han, Tae-Hyuk Kwon
  • Publication number: 20190371248
    Abstract: A display device includes a substrate, first pixels, second pixels, and third pixels. The substrate has a first pixel area, a second pixel area, and a third pixel area. The first pixels are in the first pixel area and are connected to first scan lines and first emission control lines. The second pixels are in the second pixel area and are connected to second scan lines and second emission control lines. The third pixels are in the third pixel area and are connected to third scan lines and third emission control lines. The second scan lines are spaced apart from the third scan lines, and the second emission control lines are spaced apart from the third emission control lines.
    Type: Application
    Filed: August 19, 2019
    Publication date: December 5, 2019
    Inventors: Yang Wan Kim, Seung Kyu Lee, Sun Ja Kwon, Tae Hoon Kwon, Byung Sun Kim, Hyun Ae Park, Su Jin Lee, Jae Yong Lee, Seung Ji Cha
  • Publication number: 20190360948
    Abstract: A method of analyzing fines migration in a multiphase flow in a sediment layer using X-ray computed tomography (CT) image includes, preparing an X-ray CT image analysis sample; analyzing an X-ray CT image during a depressurization process; calibrating and calculating a fines content; and estimating a fines migration analysis result.
    Type: Application
    Filed: April 22, 2019
    Publication date: November 28, 2019
    Applicant: Korea Institute Of Geoscience And Mineral Resources
    Inventors: Joo-Yong LEE, Min-Hui Lee, Gyeol Han, Tae-Hyuk Kwon
  • Publication number: 20190304356
    Abstract: A display device includes a substrate including a first pixel area, a second pixel area, and a third pixel area, each of the second and third pixel areas having a smaller surface area than the first pixel area and being connected to the first pixel area, first to third pixels provided in the first to third pixel areas, respectively, first to third lines connected to the first to third pixels, respectively, a line connecting part connecting the second and third lines, and a dummy unit overlapping the line connecting part to compensate for a difference of a load value of the first line and a load value of the second line.
    Type: Application
    Filed: June 19, 2019
    Publication date: October 3, 2019
    Inventors: Ji Hyun KA, Sun Ja KWON, Tae Hoon KWON, Byung Sun KIM, Yang Wan KIM, Hyun Ae PARK, Su Jin LEE, Seung Kyu LEE, Jae Yong LEE, Jin Tae JEONG, Seung Ji CHA
  • Patent number: 10411129
    Abstract: Methods of forming a semiconductor device may include forming a fin-type active pattern that extends in a first direction on a substrate, the fin-type active pattern including a lower pattern on the substrate and an upper pattern on the lower pattern. A field insulating layer is formed on the substrate, the sidewalls of the fin-type active pattern, and a portion upper pattern protruding further away from the substrate than a top surface of the field insulating layer. A dummy gate pattern that intersects the fin-type active pattern and that extends in a second direction that is different from the first direction is formed. The methods include forming dummy gate spacers on side walls of the dummy gate pattern, forming recesses in the fin-type active pattern on both sides of the dummy gate pattern and forming source and drain regions on both sides of the dummy gate pattern.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: September 10, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Shigenobu Maeda, Tae-Yong Kwon, Sang-Su Kim, Jae-Hoo Park
  • Patent number: 10388228
    Abstract: A display device includes a substrate, first pixels, second pixels, and third pixels. The substrate has a first pixel area, a second pixel area, and a third pixel area. The first pixels are in the first pixel area and are connected to first scan lines and first emission control lines. The second pixels are in the second pixel area and are connected to second scan lines and second emission control lines. The third pixels are in the third pixel area and are connected to third scan lines and third emission control lines. The second scan lines are spaced apart from the third scan lines, and the second emission control lines are spaced apart from the third emission control lines.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: August 20, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yang Wan Kim, Seung Kyu Lee, Sun Ja Kwon, Tae Hoon Kwon, Byung Sun Kim, Hyun Ae Park, Su Jin Lee, Jae Yong Lee, Seung Ji Cha
  • Patent number: 10354578
    Abstract: A display device includes a substrate including a first pixel area, a second pixel area, and a third pixel area, each of the second and third pixel areas having a smaller surface area than the first pixel area and being connected to the first pixel area, first to third pixels provided in the first to third pixel areas, respectively, first to third lines connected to the first to third pixels, respectively, a line connecting part connecting the second and third lines, and a dummy unit overlapping the line connecting part to compensate for a difference of a load value of the first line and a load value of the second line.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: July 16, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Ji Hyun Ka, Sun Ja Kwon, Tae Hoon Kwon, Byung Sun Kim, Yang Wan Kim, Hyun Ae Park, Su Jin Lee, Seung Kyu Lee, Jae Yong Lee, Jin Tae Jeong, Seung Ji Cha
  • Publication number: 20190145001
    Abstract: A deposition apparatus includes an upper shower head and a lower shower head within a process chamber, the upper shower head and the lower shower head facing each other, a support structure between the upper shower head and the lower shower head, the support structure being connected to the lower shower head to support a wafer, and a plasma process region between the wafer supported by the support structure and the lower shower head, wherein the lower shower head includes lower holes to jet a lower gas in a direction of the wafer, wherein the upper shower head includes upper holes to jet an upper gas in a direction of the wafer, and wherein the support structure includes through opening portions to discharge a portion of the lower gas jetted through the lower holes to a space between the support structure and the upper shower head.
    Type: Application
    Filed: May 24, 2018
    Publication date: May 16, 2019
    Inventors: Byung Sun PARK, Ji Youn SEO, Ji Woon IM, Hyun Seok LIM, Byung Ho CHUN, Yu Seon KANG, Hyuk Ho KWON, Sung Jin PARK, Tae Yong EOM, Dong Hyeop HA
  • Publication number: 20190148211
    Abstract: A deposition apparatus for depositing a material on a wafer, the apparatus including a lower shower head; an upper shower head disposed on the lower shower head, the upper shower head facing the lower shower head; and a support structure between the upper shower head and the lower shower head, the wafer being supportable by the support structure, wherein the upper shower head includes upper holes for providing an upper gas onto the wafer, the lower shower head includes lower holes for providing a lower gas onto the wafer, the support structure includes a ring body surrounding the wafer; a plurality of ring support shafts between the ring body and the lower shower head; and a plurality of wafer supports extending inwardly from a lower region of the ring body to support the wafer, and the plurality of wafer supports are spaced apart from one another.
    Type: Application
    Filed: May 31, 2018
    Publication date: May 16, 2019
    Inventors: Ji Youn SEO, Byung Sun PARK, Sung Jin PARK, Ji Woon IM, Hyun Seok LIM, Byung Ho CHUN, Yu Seon KANG, Hyuk Ho KWON, Tae Yong EOM, Dae Hun CHOI, Dong Hyeop HA
  • Publication number: 20190109214
    Abstract: A vertical tunnel field effect transistor (VTFET) including a fin structure protruding from a substrate including a source/drain region, an epitaxially-grown source/drain structure on the fin structure, a cap including pillar portions, the pillar portions covering side surfaces of the epitaxially-grown source/drain structure and partially covering side surfaces of a top portion of the fin structure, a gate insulator covering remaining portions of the side surfaces of the fin structure under the pillar portions of the cap, a work function metal gate on the gate insulator, and a separation pattern surrounding a bottom portion of a fin structure such that the work function metal gate is vertically between the cap and the separation pattern, the separation pattern electrically isolating the work function metal gate from the source/drain region, and a method of manufacturing the same may be provided.
    Type: Application
    Filed: November 21, 2018
    Publication date: April 11, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Kyung Yub JEON, Tae Yong KWON, Oh Seong KWON, Soo Yeon JEONG, Yong Hee PARK, Jong Ryeol YOO
  • Patent number: 10164057
    Abstract: A vertical tunnel field effect transistor (VTFET) including a fin structure protruding from a substrate including a source/drain region, an epitaxially-grown source/drain structure on the fin structure, a cap including pillar portions, the pillar portions covering side surfaces of the epitaxially-grown source/drain structure and partially covering side surfaces of a top portion of the fin structure, a gate insulator covering remaining portions of the side surfaces of the fin structure under the pillar portions of the cap, a work function metal gate on the gate insulator, and a separation pattern surrounding a bottom portion of a fin structure such that the work function metal gate is vertically between the cap and the separation pattern, the separation pattern electrically isolating the work function metal gate from the source/drain region, and a method of manufacturing the same may be provided.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: December 25, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung Yub Jeon, Tae Yong Kwon, Oh Seong Kwon, Soo Yeon Jeong, Yong Hee Park, Jong Ryeol Yoo
  • Publication number: 20180350952
    Abstract: A vertical tunnel field effect transistor (VTFET) including a fin structure protruding from a substrate including a source/drain region, an epitaxially-grown source/drain structure on the fin structure, a cap including pillar portions, the pillar portions covering side surfaces of the epitaxially-grown source/drain structure and partially covering side surfaces of a top portion of the fin structure, a gate insulator covering remaining portions of the side surfaces of the fin structure under the pillar portions of the cap, a work function metal gate on the gate insulator, and a separation pattern surrounding a bottom portion of a fin structure such that the work function metal gate is vertically between the cap and the separation pattern, the separation pattern electrically isolating the work function metal gate from the source/drain region, and a method of manufacturing the same may be provided.
    Type: Application
    Filed: January 24, 2018
    Publication date: December 6, 2018
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Kyung Yub JEON, Tae Yong KWON, Oh Seong KWON, Soo Yeon JEONG, Yong Hee PARK, Jong Ryeol YOO
  • Publication number: 20180315667
    Abstract: A method of fabricating a gate all around semiconductor device is provided.
    Type: Application
    Filed: December 26, 2017
    Publication date: November 1, 2018
    Inventors: Tae Yong Kwon, Oh Seong Kwon
  • Patent number: 10014300
    Abstract: An integrated circuit device as provided herein may include a device region and an inter-device isolation region. Within the device region, a fin-type active region may protrude from a substrate, and opposite sidewalls of the fin-type active region may be covered by an inner isolation layer. An outer isolation layer may fill an outer deep trench in the inter-device isolation region. The inner isolation layer may extend away from the device region at an inner sidewall of the outer deep trench and into the inter-device isolation region. There may be multiple fin-type active regions, and trenches therebetween. The outer deep trench and the trenches between the plurality of fin-type active regions may be of different heights. The integrated circuit device and methods of manufacturing described herein may reduce a possibility that various defects or failures may occur due to an unnecessary fin-type active region remaining around the device region.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: July 3, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mirco Cantoro, Tae-yong Kwon, Jae-young Park, Dong-hoon Hwang, Han-ki Lee, So-ra You
  • Publication number: 20180151736
    Abstract: Methods of forming a semiconductor device may include forming a fin-type active pattern that extends in a first direction on a substrate, the fin-type active pattern including a lower pattern on the substrate and an upper pattern on the lower pattern. A field insulating layer is formed on the substrate, the sidewalls of the fin-type active pattern, and a portion upper pattern protruding further away from the substrate than a top surface of the field insulating layer. A dummy gate pattern that intersects the fin-type active pattern and that extends in a second direction that is different from the first direction is formed. The methods include forming dummy gate spacers on side walls of the dummy gate pattern, forming recesses in the fin-type active pattern on both sides of the dummy gate pattern and forming source and drain regions on both sides of the dummy gate pattern.
    Type: Application
    Filed: January 23, 2018
    Publication date: May 31, 2018
    Inventors: Shigenobu Maeda, Tae-Yong KWON, Sang-Su KIM, Jae-Hoo PARK
  • Patent number: 9966375
    Abstract: A semiconductor device includes a compound semiconductor layer, where the compound semiconductor layer includes separate fin patterns in separate regions. The separate fin patterns may include different materials. The separate fin patterns may include different dimensions, including one or more of width and height of one or more portions of the fin patterns. The separate fin patterns may include an upper pattern and a lower pattern. The upper pattern and the lower pattern may include different materials. The upper pattern and the lower pattern may include different dimensions. Separate regions may include separate ones of an NMOS or a PMOS. The semiconductor device may include gate electrodes on the compound semiconductor layer. Separate gate electrodes may intersect the separate fin patterns.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: May 8, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Joon Choi, Tae-Yong Kwon, Mirco Cantoro, Chang-Jae Yang, Dong-Hoon Khang, Woo-Ram Kim, Cheol Kim, Seung-Jin Mun, Seung-Mo Ha, Do-Hyoung Kim, Seong-Ju Kim, So-Ra You, Woong-ki Hong