Patents by Inventor Tae Young JIN
Tae Young JIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230327845Abstract: A transceiver includes a transmitter and a receiver connected to each other through a first line and a second line. The transmitter transmits signals having a first voltage range to the first line and the second line in a first mode, and transmits signals having a second voltage range less than the first voltage range to the first line and the second line in a second mode. In transmitting a (1?1)-th payload to the receiver, the transmitter is sequentially driven in the first mode, the second mode, and the first mode, and transmits a first clock training pattern and the (1?1)-th payload in the second mode. The receiver includes a clock data recovery circuit generating a first clock signal corresponding to the received first clock training pattern and a register storing first frequency information and first phase information of the first clock training pattern.Type: ApplicationFiled: June 9, 2023Publication date: October 12, 2023Inventors: Hyun Su KIM, Dong Won PARK, Jun Dal KIM, Kyung Youl MIN, Jong Man BAE, Jun Yong SONG, Tae Young JIN
-
Publication number: 20230318860Abstract: A transmitter includes a transmission controller which outputs original data through an original data lane, an encoder which encodes the original data into encoded data and outputs the encoded data through an encoded data lane, and a transmission driver which outputs the encoded data at a speed of M (M is a real number greater than 0) gigabits per second through a transmission and reception interface. The transmission driver provides a first clock signal corresponding to an output speed to the encoder, the encoder provides a second clock signal having a second frequency less than a first frequency of the first clock signal to the transmission controller, the transmission controller outputs the original data based on the second clock signal, and the encoder outputs the encoded data based on the first clock signal.Type: ApplicationFiled: March 30, 2023Publication date: October 5, 2023Inventors: Tae Young JIN, Jun Dal KIM, Hyun Su KIM, Kyung Youl MIN, Dong Won PARK, Jong Man BAE
-
Publication number: 20230306893Abstract: A transceiver includes a transmitter and a receiver connected to each other by a first line and a second line. The transmitter transmits signals each having a first voltage range to the first line and the second line in a first mode, and signals each having a second voltage range less than the first voltage range to the first line and the second line in a second mode. The receiver includes a low-power driver which receives signals through the first line and the second line in an operating state of the first mode, and stops an operation thereof in the second mode, and a high-speed driver which receives signals through the first line and the second line in the second mode, and stops an operation thereof in the first mode.Type: ApplicationFiled: October 26, 2022Publication date: September 28, 2023Inventors: Hyun Su Kim, Dong Won Park, Jun Yong Song, Tae Young Jin
-
Patent number: 11677536Abstract: A transceiver includes a transmitter and a receiver connected to each other through a first line and a second line. The transmitter transmits signals having a first voltage range to the first line and the second line in a first mode, and transmits signals having a second voltage range less than the first voltage range to the first line and the second line in a second mode. In transmitting a (1-1)-th payload to the receiver, the transmitter is sequentially driven in the first mode, the second mode, and the first mode, and transmits a first clock training pattern and the (1-1)-th payload in the second mode. The receiver includes a clock data recovery circuit generating a first clock signal corresponding to the received first clock training pattern and a register storing first frequency information and first phase information of the first clock training pattern.Type: GrantFiled: January 13, 2022Date of Patent: June 13, 2023Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Hyun Su Kim, Dong Won Park, Jun Dal Kim, Kyung Youl Min, Jong Man Bae, Jun Yong Song, Tae Young Jin
-
Publication number: 20230170997Abstract: A transceiver includes a transmitter and a receiver which are connected to each other through a first line and a second line. The transmitter transmits a first clock training pattern to the receiver in a first period, transmits a second clock training pattern and a first first payload to the receiver in a second period, and transmits a third clock training pattern and a second first payload to the receiver in a third period. The first clock training pattern, the second clock training pattern, and the third clock training pattern are variable based on a plurality of driving modes.Type: ApplicationFiled: October 4, 2022Publication date: June 1, 2023Inventors: Dong Won PARK, Jun Dal KIM, Hyun Su KIM, Jong Man BAE, Jun Yong SONG, Tae Young JIN
-
Patent number: 11558080Abstract: A transceiver device includes a transmitter and a receiver connected through first and second lines. A first frame period includes an active period for transmitting a first payload and a vertical blank period including a frequency hopping period. The transmitter transmits, to the first and second lines, signals having a first voltage range in a first mode and signals having a second voltage range in a second mode. The transmitter generates a first horizontal synchronization signal in the second mode except for the frequency hopping period, encodes the first horizontal synchronization signal to horizontal synchronization data, and generates a second horizontal synchronization signal in the first mode in the frequency hopping period. The transmitter adds a first clock training pattern to the horizontal synchronization data except for the frequency hopping period, and adds a second clock training pattern to first horizontal synchronization data after the frequency hopping period.Type: GrantFiled: January 14, 2022Date of Patent: January 17, 2023Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Tae Young Jin, Dong Won Park, Jun Dal Kim, Hyun Su Kim, Kyung Youl Min, Jong Man Bae, Jun Yong Song
-
Publication number: 20220416841Abstract: A transceiver device includes a transmitter and a receiver connected through first and second lines. A first frame period includes an active period for transmitting a first payload and a vertical blank period including a frequency hopping period. The transmitter transmits, to the first and second lines, signals having a first voltage range in a first mode and signals having a second voltage range in a second mode. The transmitter generates a first horizontal synchronization signal in the second mode except for the frequency hopping period, encodes the first horizontal synchronization signal to horizontal synchronization data, and generates a second horizontal synchronization signal in the first mode in the frequency hopping period. The transmitter adds a first clock training pattern to the horizontal synchronization data except for the frequency hopping period, and adds a second clock training pattern to first horizontal synchronization data after the frequency hopping period.Type: ApplicationFiled: January 14, 2022Publication date: December 29, 2022Inventors: Tae Young JIN, Dong Won PARK, Jun Dal KIM, Hyun Su KIM, Kyung Youl MIN, Jong Man BAE, Jun Yong SONG
-
Publication number: 20220397931Abstract: A transceiver includes a transmitter and a receiver connected to each other by a first line and a second line. The transmitter transmits signals having a first voltage range to the first line and the second line in a first mode, and transmits signals having a second voltage range smaller than the first voltage range to the first line and the second line in a second mode. The transmitter encodes an original payload in the second mode to generate a first payload, and transmits the clock training pattern and the first payload through the first line and the second line.Type: ApplicationFiled: January 12, 2022Publication date: December 15, 2022Inventors: Jun Yong SONG, Jong Man BAE, Jun Dal KIM, Hyun Su KIM, Kyung Youl MIN, Dong Won PARK, Tae Young JIN
-
Publication number: 20220397932Abstract: A data receiver, which communicates with a data transmitter through a plurality of lanes, includes: a first reception unit which receives first data through a first lane; a second reception unit which receives second data through a second lane; and a detector which compares the first data and the second data to detect a skew between the first lane and the second lane. The first reception unit includes a first clock data recovery unit which recovers a first clock and first payload data from the first data. The first reception unit controls a loop speed of the first clock data recovery unit based on a skew level of the skew.Type: ApplicationFiled: March 25, 2022Publication date: December 15, 2022Inventors: Jun Dal KIM, Dong Won PARK, Hyun Su KIM, Kyung Youl MIN, Jong Man BAE, Jun Yong SONG, Tae Young JIN
-
Publication number: 20220399986Abstract: A transceiver includes a transmitter and a receiver connected to each other through a first line and a second line. The transmitter transmits signals having a first voltage range to the first line and the second line in a first mode, and transmits signals having a second voltage range less than the first voltage range to the first line and the second line in a second mode. In transmitting a (1-1)-th payload to the receiver, the transmitter is sequentially driven in the first mode, the second mode, and the first mode, and transmits a first clock training pattern and the (1-1)-th payload in the second mode. The receiver includes a clock data recovery circuit generating a first clock signal corresponding to the received first clock training pattern and a register storing first frequency information and first phase information of the first clock training pattern.Type: ApplicationFiled: January 13, 2022Publication date: December 15, 2022Inventors: Hyun Su KIM, Dong Won PARK, Jun Dal KIM, Kyung Youl MIN, Jong Man BAE, Jun Yong SONG, Tae Young JIN