Patents by Inventor Taebok Jung

Taebok Jung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7674640
    Abstract: A stacked die package system including forming a bottom package including a bottom substrate and a bottom die mounted and electrically connected under the bottom substrate and forming a top package including a top substrate and a top die mounted and electrically connected over the top substrate. Mounting the top package by the top substrate over the bottom substrate and electrically connecting the bottom and top substrates. Mounting system electrical connectors under the bottom substrate adjacent the bottom die.
    Type: Grant
    Filed: August 24, 2007
    Date of Patent: March 9, 2010
    Assignee: STATS ChipPAC Ltd.
    Inventors: Jong-Woo Ha, Myung Kil Lee, Hyun Uk Kim, Taebok Jung
  • Patent number: 7436048
    Abstract: A multichip package has a leadframe including peripheral leads arranged about a centrally situated die paddle. A first die is attached to a first side of the leadframe die paddle. The second side of the leadframe is partially cut away so that an outer part of the die paddle is thinner, and an inner part of the leads is thinner. These partially cutaway portions in the second side of the leadframe provide a cavity, in which a second die is attached active side upward. The lower die may have bond pads near the center of the active surface, and electrical interconnection of the lower die may be made by wire bonds running through the gap between the die paddle and the leads; or, the lower die may be attached, and electrically interconnected, by flip chip interconnect to the die attach side of the cavity in the leadframe.
    Type: Grant
    Filed: March 14, 2007
    Date of Patent: October 14, 2008
    Assignee: Chippac, Inc.
    Inventors: Jongwoo Ha, Taebok Jung
  • Publication number: 20070284718
    Abstract: A stacked die package system including forming a bottom package including a bottom substrate and a bottom die mounted and electrically connected under the bottom substrate and forming a top package including a top substrate and a top die mounted and electrically connected over the top substrate. Mounting the top package by the top substrate over the bottom substrate and electrically connecting the bottom and top substrates. Mounting system electrical connectors under the bottom substrate adjacent the bottom die.
    Type: Application
    Filed: August 24, 2007
    Publication date: December 13, 2007
    Inventors: Jong-Woo Ha, Myung Lee, Hyun Kim, Taebok Jung
  • Patent number: 7279785
    Abstract: A stacked die package system including forming a bottom package including a bottom substrate and a bottom die mounted and electrically connected under the bottom substrate and forming a top package including a top substrate and a top die mounted and electrically connected over the top substrate. Mounting the top package by the top substrate over the bottom substrate and electrically connecting the bottom and top substrates. Mounting system electrical connectors under the bottom substrate adjacent the bottom die.
    Type: Grant
    Filed: November 12, 2005
    Date of Patent: October 9, 2007
    Assignee: Stats Chippac Ltd.
    Inventors: Jong-Woo Ha, Myung Kil Lee, Hyun Uk Kim, Taebok Jung
  • Publication number: 20070152308
    Abstract: A multichip package has a leadframe including peripheral leads arranged about a centrally situated die paddle. A first (“upper”) die is attached to a first (“top”) side of the leadframe die paddle, which can be generally flat. The second (“bottom”) side of the leadframe is partially cut away (such as by partial etching), so that an outer part of the die paddle is thinner, and so that an inner part of the leads is thinner. These partially cutaway portions in the second (‘bottom”) side of the leadframe provide a cavity, in which a second (“lower”) die is attached active side upward. The lower die may have bond pads situated near the center of the active surface, and electrical interconnection of the lower die may be made by wire bonds running through the gap between the die paddle and the leads; or, the lower die may be attached, and electrically interconnected, by flip chip interconnect to the die attach side of the cavity in the leadframe.
    Type: Application
    Filed: March 14, 2007
    Publication date: July 5, 2007
    Applicant: ChipPAC, Inc
    Inventors: Jongwoo Ha, Taebok Jung
  • Patent number: 7208821
    Abstract: A multichip package has a leadframe including peripheral leads arranged about a centrally situated die paddle. A first (“upper”) die is attached to a first (“top”) side of the leadframe die paddle, which can be generally flat. The second (“bottom”) side of the leadframe is partially-cut away (such as by partial etching), so that an outer part of the die paddle is thinner, and so that an inner part of the leads is thinner. These partially cutaway portions in the second (“bottom”) side of the leadframe provide a cavity, in which a second (“lower”) die is attached active side upward. The lower die may have bond pads situated near the center of the active surface, and electrical interconnection of the lower die may be made by wire bonds running through the gap between the die paddle and the leads; or, the lower die may be attached, and electrically interconnected, by flip chip interconnect to the die attach side of the cavity in the leadframe.
    Type: Grant
    Filed: October 17, 2005
    Date of Patent: April 24, 2007
    Assignee: ChipPAC, Inc.
    Inventors: Jongwoo Ha, Taebok Jung
  • Publication number: 20060180914
    Abstract: A stacked die package system including forming a bottom package including a bottom substrate and a bottom die mounted and electrically connected under the bottom substrate and forming a top package including a top substrate and a top die mounted and electrically connected over the top substrate. Mounting the top package by the top substrate over the bottom substrate and electrically connecting the bottom and top substrates. Mounting system electrical connectors under the bottom substrate adjacent the bottom die.
    Type: Application
    Filed: November 12, 2005
    Publication date: August 17, 2006
    Applicant: STATS CHIPPAC LTD.
    Inventors: Jong-Woo Ha, Myung Kil Lee, Hyun Uk Kim, Taebok Jung
  • Publication number: 20060081967
    Abstract: A multichip package has a leadframe including peripheral leads arranged about a centrally situated die paddle. A first (“upper”) die is attached to a first (“top”) side of the leadframe die paddle, which can be generally flat. The second (“bottom”) side of the leadframe is partially-cut away (such as by partial etching), so that an outer part of the die paddle is thinner, and so that an inner part of the leads is thinner. These partially cutaway portions in the second (“bottom”) side of the leadframe provide a cavity, in which a second (“lower”) die is attached active side upward. The lower die may have bond pads situated near the center of the active surface, and electrical interconnection of the lower die may be made by wire bonds running through the gap between the die paddle and the leads; or, the lower die may be attached, and electrically interconnected, by flip chip interconnect to the die attach side of the cavity in the leadframe.
    Type: Application
    Filed: October 17, 2005
    Publication date: April 20, 2006
    Applicant: ChipPAC, Inc
    Inventors: Jongwoo Ha, Taebok Jung