Abstract: A storage device is included. The storage device includes: a memory device including a plurality of planes, wherein each of the plurality of planes is provided in one of a plurality of banks of the memory device; and a memory controller configured to: receive, from a host, a plurality of jobs to be performed on the memory device, the plurality of jobs including a plane-level job to be performed in a plane from among the plurality of planes; determine, for each of the plurality of planes at a first time, a target bank from among the plurality of banks based on plane information associated with a job from among the plurality of jobs that is pending in the storage device; and transmit the job for the target bank to the memory device.

Abstract: A nonvolatile memory device that includes a memory cell array including a plurality of nonvolatile memory cells; a page buffer circuit connected to the memory cell array; a status data memory circuit storing a first plurality of status data items; a control logic circuit controlling the status data memory circuit to accumulate the first plurality of status data items in the page buffer circuit, in response to a first status data group read command provided from an external device; and an input/output circuit outputting the first plurality of status data items accumulated in the page buffer circuit to the external device.

Abstract: A nonvolatile memory device that includes a memory cell array including a plurality of nonvolatile memory cells; a page buffer circuit connected to the memory cell array; a status data memory circuit storing a first plurality of status data items; a control logic circuit controlling the status data memory circuit to accumulate the first plurality of status data items in the page buffer circuit, in response to a first status data group read command provided from an external device; and an input/output circuit outputting the first plurality of status data items accumulated in the page buffer circuit to the external device.

Abstract: A storage controller included in a storage device, the storage controller including an interrupt circuit that detects a sudden power off (SPO) with respect to the storage device, and issues a SPO notification and an emergency flush request; a central processing unit that receives the SPO notification and issues a program request; and a volatile memory device including a plurality of memory areas. A first non-volatile memory (NVM) interfacing circuit of the storage device programs data stored in a first memory area from among the plurality of memory areas to an external first non-volatile memory device in response to receiving the program request, and programs data stored in a second memory from area among the plurality of memory areas to the first non-volatile memory device in response to receiving the emergency flush request.

Abstract: A controller of a storage system, includes a plurality of modules each including an intellectual property (IP) module and a core module, wherein, based on the IP module operating as a master for a first module of the plurality of modules, an idle clock of the first module is a first clock, wherein based on the core module operating as a master for a second module of the plurality of modules, an idle clock of the second module is a second clock, wherein a clock frequency of the first clock is greater than zero and smaller than a maximum clock frequency, and wherein a clock frequency of the second clock is zero.

Abstract: A controller of a storage system, includes a plurality of modules each including an intellectual property (IP) module and a core module, wherein, based on the IP module operating as a master for a first module of the plurality of modules, an idle clock of the first module is a first clock, wherein based on the core module operating as a master for a second module of the plurality of modules, an idle clock of the second module is a second clock, wherein a clock frequency of the first clock is greater than zero and smaller than a maximum clock frequency, and wherein a clock frequency of the second clock is zero.

Abstract: A program method of a multi-bit memory device is provided. First page data is programmed in a first region of a memory cell array. The first page data is stored in a first buffer of a page buffer. Second page data is programmed in the first region of the memory cell array. The second page data is stored in a third buffer of the page buffer. Third page data is stored in the first region of the memory cell array. The second page data stored in the third buffer is transferred to a second buffer of the page buffer and the third page data is stored in the third buffer. The first to third page data stored in page buffer are programmed in a second region of the memory cell array.

Abstract: A program method of a multi-bit memory device is provided. First page data is programmed in a first region of a memory cell array. The first page data is stored in a first buffer of a page buffer. Second page data is programmed in the first region of the memory cell array. The second page data is stored in a third buffer of the page buffer. Third page data is stored in the first region of the memory cell array. The second page data stored in the third buffer is transferred to a second buffer of the page buffer and the third page data is stored in the third buffer. The first to third page data stored in page buffer are programmed in a second region of the memory cell array.