Abstract: An ultrasound probe, including a transducer module configured to receive an echo ultrasound signal reflected from a subject in response to a transmitted ultrasound signal, and a driver chip provided in the transducer module, the driver chip being configured to focus at least one of the ultrasound signal and the echo ultrasound signal, wherein the driver chip includes a fine analog beamformer configured to apply a fine delay and a coarse analog beamformer configured to apply a coarse delay, wherein the fine analog beamformer is arranged in a first inner region of a plurality of inner regions of the driver chip, the first inner region being located opposite to the transducer module, and wherein the coarse analog beamformer is arranged in a second inner region of the plurality of inner regions of the driver chip, the second inner region being different from the first inner region.

Abstract: Provided are an ultrasonic probe and a method of manufacturing the same. The method includes: forming a plurality of grooves by removing regions of a first insulating layer and a first silicon wafer from a first substrate including the first silicon wafer and the first insulating layer; bonding a second substrate including a second silicon wafer, a second insulating layer, and a silicon thin layer to the first substrate, such that the plurality of grooves turn into a plurality of cavities; removing the second silicon wafer from the second substrate; forming transducer cells on regions of the second insulating layer corresponding to the plurality of cavities; and forming a plurality of unit substrates by cutting the first substrate, the silicon thin layer, and the second insulating layer.

Abstract: Provided is a method for forming a thin film. The method for forming the thin film includes forming a first thin film having a first thickness with first crystallinity through an atomic layer deposition process and etching the first thin film by a predetermined thickness through an atomic layer etching process with respect to the first thin film to form a second thin film having a second thickness less than the first thickness.

Abstract: Provided are a substrate processing apparatus and a substrate processing method using the same and, more particularly, a substrate processing apparatus capable of controlling deposition of a reactive-metal-containing precursor in an exhaust line, and a substrate processing method using the same.

Abstract: Provided is a method for forming a thin film. The method for forming the thin film includes forming a first thin film having a first thickness with first crystallinity through an atomic layer deposition process and etching the first thin film by a predetermined thickness through an atomic layer etching process with respect to the first thin film to form a second thin film having a second thickness less than the first thickness.

Abstract: There are provided an ultrasonic apparatus and a beamforming method for the ultrasonic apparatus. According to an aspect, an ultrasonic apparatus includes a 2D array transducer in which a plurality of elements are arranged in a plurality of rows and columns; a signal supplier configured to supply an ultrasonic signal to the 2D array transducer; a first delayer configured to delay the ultrasonic signal to output a plurality of first delay signals corresponding to any one of the number of rows and the number of columns; and a second delayer configured to delay one of the plurality of first delay signals to output a plurality of second delay signals corresponding to the other one of the number of rows and the number of columns, and transmit the plurality of second delay signals to the 2D array transducer.

Abstract: Provided is a method of controlling an operation of a channel including at least one transducer, which includes comparing a voltage corresponding to current flowing into the channel to a threshold voltage and controlling the operation of the channel based on a result of the comparing.

Abstract: An ultrasound probe, including a transducer module configured to receive an echo ultrasound signal reflected from a subject in response to a transmitted ultrasound signal, and a driver chip provided in the transducer module, the driver chip being configured to focus at least one of the ultrasound signal and the echo ultrasound signal, wherein the driver chip includes a fine analog beamformer configured to apply a fine delay and a coarse analog beamformer configured to apply a coarse delay, wherein the fine analog beamformer is arranged in a first inner region of a plurality of inner regions of the driver chip, the first inner region being located opposite to the transducer module, and wherein the coarse analog beamformer is arranged in a second inner region of the plurality of inner regions of the driver chip, the second inner region being different from the first inner region.

Abstract: Provided are an ultrasonic probe and a method of manufacturing the same. The method includes: forming a plurality of grooves by removing regions of a first insulating layer and a first silicon wafer from a first substrate including the first silicon wafer and the first insulating layer; bonding a second substrate including a second silicon wafer, a second insulating layer, and a silicon thin layer to the first substrate, such that the plurality of grooves turn into a plurality of cavities; removing the second silicon wafer from the second substrate; forming transducer cells on regions of the second insulating layer corresponding to the plurality of cavities; and forming a plurality of unit substrates by cutting the first substrate, the silicon thin layer, and the second insulating layer.

Abstract: Provided are a substrate processing apparatus and a substrate processing method using the same and, more particularly, a substrate processing apparatus capable of controlling deposition of a reactive-metal-containing precursor in an exhaust line, and a substrate processing method using the same.

Abstract: A display apparatus and driving method are discussed where the ultrasonic imaging apparatus includes an ultrasonic transducer configured to sequentially output a first ultrasonic signal, a second ultrasonic signal, and a third ultrasonic signal; a beamforming unit configured to generate a first synthesized signal by delaying the first ultrasonic signal and synthesizing the delayed first ultrasonic signal with the second ultrasonic signal, and to generate a second synthesized signal by delaying the first synthesized signal and synthesizing the delayed first synthesized signal with the third ultrasonic signal.

Abstract: Provided is a method of controlling an operation of a channel including at least one transducer, which includes comparing a voltage corresponding to current flowing into the channel to a threshold voltage and controlling the operation of the channel based on a result of the comparing.

Abstract: A semiconductor memory device includes a memory cell array configured to include memory cells, peripheral circuits configured to read out data stored in a selected memory cell in a read operation, and a controller configured to control the peripheral circuits so that the peripheral circuits sense a voltage level of the bit line when a first read voltage of the read voltages is supplied to the word line and the peripheral circuits sense voltage levels of the bit line when a second read voltage lower than the first read voltage by a specific level and a third read voltage higher than the first read voltage by the specific level are supplied to the word line in order to determine whether a threshold voltage of the selected memory cell falls within a set voltage distribution in the read operation.

Abstract: A semiconductor device includes a first operation circuit configured to generate addition data by adding a column address and a page address and output a remainder obtained by dividing the addition data by a set value as seed data, a mask data output circuit configured to output mask data corresponding to the respective seed data, and a second operation circuit configured to generate random data by performing a logic operation on the mask data and program data corresponding to the column and page addresses.

Abstract: A semiconductor memory device includes memory cells arranged at regions where word lines and bit lines cross each other; a randomizing and de-randomizing circuit configured to perform a first randomizing operation on data to be programmed to the memory cells, based on a seed value, so as to generate first randomized data; a data reading/writing circuit configured to perform a second randomizing operation on the first randomized data using a data inverting operation so as to generate second randomized data and program the second randomized data to the memory cells; and a control logic configured to control the randomizing and de-randomizing circuit and the data reading/writing circuit.

Abstract: A semiconductor memory device is configured to internally perform a test operation utilizing a random data pattern. The semiconductor memory device includes a random data pattern test unit that operates under control of on-board control logic that also manages normal operation of the semiconductor memory device. The control logic controls test operation of the semiconductor memory device in response to simple commands received from an external device. Therefore, the test time may be reduced more than when a test is entirely controlled by an external device. Furthermore, since the external device does not need to manage the random data pattern, the test cost may be reduced more than when a test is performed under control of the external device.

Abstract: A semiconductor memory device includes memory cells arranged at regions where word lines and bit lines cross each other; a randomizing and de-randomizing circuit configured to perform a first randomizing operation on data to be programmed to the memory cells, based on a seed value, so as to generate first randomized data; a data reading/writing circuit configured to perform a second randomizing operation on the first randomized data using a data inverting operation so as to generate second randomized data and program the second randomized data to the memory cells; and a control logic configured to control the randomizing and de-randomizing circuit and the data reading/writing circuit.

Abstract: A semiconductor device includes a first operation circuit configured to generate addition data by adding a column address and a page address and output a remainder obtained by dividing the addition data by a set value as seed data, a mask data output circuit configured to output mask data corresponding to the respective seed data, and a second operation circuit configured to generate random data by performing a logic operation on the mask data and program data corresponding to the column and page addresses.

Abstract: A semiconductor memory device includes a memory cell array configured to include memory cells, peripheral circuits configured to read out data stored in a selected memory cell in a read operation, and a controller configured to control the peripheral circuits so that the peripheral circuits sense a voltage level of the bit line when a first read voltage of the read voltages is supplied to the word line and the peripheral circuits sense voltage levels of the bit line when a second read voltage lower than the first read voltage by a specific level and a third read voltage higher than the first read voltage by the specific level are supplied to the word line in order to determine whether a threshold voltage of the selected memory cell falls within a set voltage distribution in the read operation.

Abstract: Disclosed is a neural stimulator for neural prosthesis: including a power receiver which receives power from outside and supplies the received power to a circuitry including an electrical signal generator; the electrical signal generator which generates a neural stimulating electrical signal; and a casing which protects the power receiver and the electrical signal generator from bodily fluid, wherein the power supplied by the power receiver to the circuitry including the electrical signal generator is AC logic power. In accordance with this disclosure, a neural stimulator with reduced production cost, simplified production process and reduced size, as compared with those of the related art, while being safe, may be provided.