Abstract: A memory device includes a memory cell array connected to a plurality of word lines, a clock generator configured to generate a clock signal, a charge pump circuit configured to generate a voltage to be provided to the plurality of word lines, based on the clock signal, a row decoder configured to provide the voltage to a selected memory block, a current generation circuit connected in parallel to a word line path through which the voltage is provided from the charge pump circuit to the row decoder and configured to generate a current flowing through the word line path for a reference time, and a defect detection circuit configured to detect a defect on the word line path by comparing a first count value of the clock signal counted before the reference time with a second count value of the clock signal counted after the reference time.

Abstract: A memory device, including a first chip including a memory cell array; and a second chip bonded to the first chip and including a voltage generator configured to generate a voltage which is supplied to the memory cell array, wherein the second chip comprises a bonding pad connected to the voltage generator and bonded to an external charge pump.

Abstract: A semiconductor device includes a first semiconductor chip; a second semiconductor chip stacked on the first semiconductor chip, wherein a type of the second semiconductor chip is different from a type of the first semiconductor chip; and a crack detection circuit including: a first crack detection line repeatedly passing through an interface between the first semiconductor chip and the second semiconductor chip; a second crack detection line including a bonding pad or a through-via structure contacting a surface of the second semiconductor chip opposite to the interface; and a crack detector in the second semiconductor chip, the crack detector being configured to output a first test signal to the first crack detection line, receive a first reception signal from the first crack detection line, output a second test signal to the second crack detection line, and receive a second reception signal from the second crack detection line.

Abstract: A memory device is provided. The memory device includes: a first cell region provided in a first layer and including a first bit line and a first redundant bit line; a second cell region provided in a second layer and including a second bit line and a second redundant bit line; a peripheral region provided in a third layer and including first page buffers configured to be respectively connected to the first bit line and the second bit line, and a second page buffer configured to be commonly connected to the first redundant bit line and the second redundant bit line; and a control circuit configured to: based on the first bit line being defective, replace the first bit line with the first redundant bit line; and based on the second bit line being defective, replace the second bit line with the second redundant bit line.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes: forming a first structure on a first wafer; forming a second structure on a second wafer including second chip regions and a second scribe lane region surrounding the second chip regions; separating first ones of the second chip regions in a central portion of the second wafer in a plan view by a first dicing process; bonding the first ones of the second chip regions with the first wafer; separating second ones of the second chip regions in an edge portion of the second wafer in a plan view by a second dicing process; bonding the second ones of the second chip regions with the first wafer, and separating the bonded first and second wafers by a third dicing process.

Abstract: The present invention relates to isolated nucleic acid molecules, comprising a functional mammalian EGR-1 (early growth response protein 1) promoter region that is operatively linked to a gene encoding a fluorescent protein and controls expression of said gene. The present invention further relates to nucleic acid vectors, comprising said nucleic, cells comprising said nucleic acids or vectors, being capable of sensing and indicating fluid shear stress acting on themselves, and methods of generating the same. Furthermore, the present invention relates to methods of evaluating fluid shear stress acting on cells in real-time during the operation of a biotechnological device or system, methods of evaluating a biotechnological device or system with respect to fluid shear stress acting on cells caused by operation of said device or system, and methods of designing a biotechnological device or system, said methods using said cells.

Abstract: A memory device includes a first memory area including a first memory cell array having a plurality of first memory cells each for storing N-bit data according to an M-bit data access scheme, where N is a natural number, and a first peripheral circuit for controlling the first memory cells and disposed below the first memory cell array, a second memory area including a second memory cell array having a plurality of second memory cells each for storing M-bit data according to an M-bit data access scheme, where M is a natural number greater than N, and a second peripheral circuit for controlling the second memory cells and disposed below the second memory cell array, the first memory area and the second memory area are included in a single semiconductor chip and share an input and output interface, and a controller configured to generate calculation data by applying a weight stored in the first memory area to sensing data in response to receiving the sensing data obtained by an external sensor, and store the ca

Abstract: A memory device includes a memory cell array, a row decoder connected to the memory cell array by a plurality of string selection lines, a plurality of word lines, and a plurality of ground selection lines, and a common source line driver connected to the memory cell array by a common source line. The memory cell array is located in an upper chip, at least a portion of the row decoder is located in a lower chip, at least a portion of the common source line driver is located in the upper chip, and a plurality of upper bonding pads of the upper chip are connected to a plurality of lower bonding pads of the lower chip to connect the upper chip to the lower chip.

Abstract: A memory device includes a memory cell array, a row decoder connected to the memory cell array by a plurality of string selection lines, a plurality of word lines, and a plurality of ground selection lines, and a common source line driver connected to the memory cell array by a common source line. The memory cell array is located in an upper chip, at least a portion of the row decoder is located in a lower chip, at least a portion of the common source line driver is located in the upper chip, and a plurality of upper bonding pads of the upper chip are connected to a plurality of lower bonding pads of the lower chip to connect the upper chip to the lower chip.

Abstract: A non-volatile memory device includes a substrate, a memory cell string including a vertical channel structure and memory cells, a voltage generator including a first transistor and configured to provide various voltages to the memory cells, and a vertical capacitor structure. The vertical capacitor structure includes first and second active patterns apart from each other in a first horizontal direction, a first gate pattern located above a channel region between the first and second active patterns, a first gate insulating film between the first gate pattern and the substrate in a vertical direction, and capacitor electrodes each extending in the vertical direction. The first transistor includes a second gate pattern and a second gate insulating film between the second gate pattern and the substrate in the vertical direction. The first gate insulating film has a thickness greater than a thickness of the second gate insulating film in the vertical direction.

Abstract: A memory device comprises a first memory area including a first memory cell array having a plurality of first memory cells each for storing N-bit data, where N is a natural number, and a first peripheral circuit for controlling the first memory cells according to an N-bit data access scheme and disposed below the first memory cell array, a second memory area including a second memory cell array having a plurality of second memory cells each for storing M-bit data, where M is a natural number greater than N, and a second peripheral circuit for controlling the second memory cells according to an M-bit data access scheme and disposed below the second memory cell array, wherein the first memory area and the second memory area are included in a single semiconductor chip and share an input and output interface, and a controller configured to generate calculation data by applying a weight stored in the first memory area to sensing data in response to receiving the sensing data obtained by an external sensor, and sto

Abstract: A memory device includes; a memory area including a first memory area including first memory cells storing N-bit data and a second memory area including second memory cells storing M-bit data, where ‘M’ and ‘N’ are natural numbers and M is greater than N, and a controller configured to read data stored in the first memory area using a first read operation, read data stored in the second memory area using a second read operation different from the first read operation, and selectively store data in one of the first memory area and the second memory area based on a frequency of use (FOU) of the data.

Abstract: A memory device comprises a memory cell region including a first metal pad, and a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, wherein the memory cell region includes a first memory area having first memory cells storing N-bit data and a second memory area having second memory cells storing M-bit data, where ‘M’ and ‘N’ are natural numbers and M is greater than N, and the peripheral circuit region includes a controller configured to read data stored in the first memory area using a first read operation, read data stored in the second memory area using a second read operation different from the first read operation, and selectively store data in one of the first memory area and the second memory area based on a frequency of use (FOU) of the data.

Abstract: A memory device comprises a first memory area including a first memory cell array having a plurality of first memory cells each for storing N-bit data, where N is a natural number, and a first peripheral circuit for controlling the first memory cells according to an N-bit data access scheme and disposed below the first memory cell array, a second memory area including a second memory cell array having a plurality of second memory cells each for storing M-bit data, where M is a natural number greater than N, and a second peripheral circuit for controlling the second memory cells according to an M-bit data access scheme and disposed below the second memory cell array, wherein the first memory area and the second memory area are included in a single semiconductor chip and share an input and output interface, and a controller configured to generate calculation data by applying a weight stored in the first memory area to sensing data in response to receiving the sensing data obtained by an external sensor, and sto

Abstract: A memory device includes; a memory area including a first memory area including first memory cells storing N-bit data and a second memory area including second memory cells storing M-bit data, where ‘M’ and ‘N’ are natural numbers and M is greater than N, and a controller configured to read data stored in the first memory area using a first read operation, read data stored in the second memory area using a second read operation different from the first read operation, and selectively store data in one of the first memory area and the second memory area based on a frequency of use (FOU) of the data.

Abstract: A memory device comprises a memory cell region including a first metal pad, and a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, wherein the memory cell region includes a first memory area having first memory cells storing N-bit data and a second memory area having second memory cells storing M-bit data, where ‘M’ and ‘N’ are natural numbers and M is greater than N, and the peripheral circuit region includes a controller configured to read data stored in the first memory area using a first read operation, read data stored in the second memory area using a second read operation different from the first read operation, and selectively store data in one of the first memory area and the second memory area based on a frequency of use (FOU) of the data.

Abstract: A memory device includes a first memory area including a first memory cell array having a plurality of first memory cells each for storing N-bit data according to an M-bit data access scheme, where N is a natural number, and a first peripheral circuit for controlling the first memory cells and disposed below the first memory cell array, a second memory area including a second memory cell array having a plurality of second memory cells each for storing M-bit data according to an M-bit data access scheme, where M is a natural number greater than N, and a second peripheral circuit for controlling the second memory cells and disposed below the second memory cell array, the first memory area and the second memory area are included in a single semiconductor chip and share an input and output interface, and a controller configured to generate calculation data by applying a weight stored in the first memory area to sensing data in response to receiving the sensing data obtained by an external sensor, and store the ca

Abstract: A memory device includes a memory cell array, a row decoder connected to the memory cell array by a plurality of string selection lines, a plurality of word lines, and a plurality of ground selection lines, and a common source line driver connected to the memory cell array by a common source line. The memory cell array is located in an upper chip, at least a portion of the row decoder is located in a lower chip, at least a portion of the common source line driver is located in the upper chip, and a plurality of upper bonding pads of the upper chip are connected to a plurality of lower bonding pads of the lower chip to connect the upper chip to the lower chip.

Abstract: A memory device includes a memory cell array, a row decoder connected to the memory cell array by a plurality of string selection lines, a plurality of word lines, and a plurality of ground selection lines, and a common source line driver connected to the memory cell array by a common source line. The memory cell array is located in an upper chip, at least a portion of the row decoder is located in a lower chip, at least a portion of the common source line driver is located in the upper chip, and a plurality of upper bonding pads of the upper chip are connected to a plurality of lower bonding pads of the lower chip to connect the upper chip to the lower chip.

Abstract: A non-volatile memory device includes a substrate, a memory cell string including a vertical channel structure and memory cells, a voltage generator including a first transistor and configured to provide various voltages to the memory cells, and a vertical capacitor structure. The vertical capacitor structure includes first and second active patterns apart from each other in a first horizontal direction, a first gate pattern located above a channel region between the first and second active patterns, a first gate insulating film between the first gate pattern and the substrate in a vertical direction, and capacitor electrodes each extending in the vertical direction. The first transistor includes a second gate pattern and a second gate insulating film between the second gate pattern and the substrate in the vertical direction. The first gate insulating film has a thickness greater than a thickness of the second gate insulating film in the vertical direction.