Abstract: A user device is provided. The device includes a main power supply, and an auxiliary power supply. The main power supply provides a main power. The auxiliary power supply cuts off the main power according to a power level of the main power supply and provides an auxiliary power upon Sudden Power-Off (SPO).

Abstract: A user device is provided. The device includes a main power supply, and an auxiliary power supply. The main power supply provides a main power. The auxiliary power supply cuts off the main power according to a power level of the main power supply and provides an auxiliary power upon Sudden Power-Off (SPO).

Abstract: A semiconductor memory device includes a memory cell array, a word line voltage generation circuit, a row decoder, a first switching circuit, and a second switching circuit. The first switching circuit is coupled to an output terminal of the word line voltage generation circuit, and supplies an external test voltage to the word line voltage output terminal. The second switching circuit is coupled between the first switching circuit and the word line voltage output terminal, and interrupts a current path from the word line voltage output terminal to the first switching circuit when a voltage level of the word line voltage output terminal is higher than that of a power supply voltage.

Abstract: A nonvolatile memory having a memory field and a redundant field within a single semiconductor chip is disclosed. The memory field is provided to store normal data and the redundant field is provided to store essential device data. The nonvolatile memory includes a plurality of first page buffers performing a multi-bit reading operation for the memory field and a plurality of second page buffers performing a regular single-bit operation for the redundant field. A time period of the regular single-bit operation for the redundant field is shorter than that of the multi-bit operation for the memory field. The nonvolatile semiconductor memory of the invention is therefore capable of performing single-bit operation at a higher speed than the conventional nonvolatile semiconductor memories each having the single- and multi-bit operation modes, improving their performance.