Abstract: A method of rapidly cooling a high temperature vehicle coolant is disclosed. The method includes determining a coolant temperature lowering entry condition by detecting information on the coolant temperature, an engine speed, and a gear state and determining whether the coolant temperature needs to be rapidly lowered on the basis of the detected information; and changing a number of gear stages by adjusting the number of gear stages of a transmission to be reduced to a specific number of gear stages when the coolant temperature needs to be rapidly lowered in the determining of the coolant temperature lowering entry condition, so that the cooling fan is driven by driving the fan belt through a crank damper pulley using the increased engine speed according to the reducing adjustment of the number of gear stages.

Abstract: A method of rapidly cooling a high temperature vehicle coolant is disclosed. The method includes determining a coolant temperature lowering entry condition by detecting information on the coolant temperature, an engine speed, and a gear state and determining whether the coolant temperature needs to be rapidly lowered on the basis of the detected information; and changing a number of gear stages by adjusting the number of gear stages of a transmission to be reduced to a specific number of gear stages when the coolant temperature needs to be rapidly lowered in the determining of the coolant temperature lowering entry condition, so that the cooling fan is driven by driving the fan belt through a crank damper pulley using the increased engine speed according to the reducing adjustment of the number of gear stages.

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices are provided. The semiconductor devices may include a fin disposed on a substrate. The fin may include an insulating layer pattern disposed in a top surface of the fin. The semiconductor devices may also include a wire pattern disposed on the insulating layer pattern to be separated from the insulating layer pattern and a gate electrode surrounding the wire pattern.

Abstract: There is provided a method of manufacturing a semiconductor device including: preparing a semiconductor substrate having an active region; forming a dielectric layer for gate insulation on the active region; forming a curing layer with a material containing germanium (Ge) on the dielectric layer; heat-treating the curing layer; and removing the curing layer. The germanium-containing material may be silicon germanium (SiGe) or germanium (Ge).

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices are provided. The semiconductor devices may include a fin disposed on a substrate. The fin may include an insulating layer pattern disposed in a top surface of the fin. The semiconductor devices may also include a wire pattern disposed on the insulating layer pattern to be separated from the insulating layer pattern and a gate electrode surrounding the wire pattern.

Abstract: A semiconductor device includes a substrate including an NMOS region, a fin active region protruding from the substrate in the NMOS region, the fin active region including an upper surface and a sidewall, a gate dielectric layer on the upper surface and the sidewall of the fin active region, a first metal gate electrode on the gate dielectric layer, the first metal gate electrode having a first thickness at the upper surface of the fin active region and a second thickness at the sidewall of the fin active region, and a second metal gate electrode on the first metal gate electrode, the second metal gate electrode having a third thickness at the upper surface of the fin active region and a fourth thickness at the sidewall of the fin active region, wherein the third thickness is less than the fourth thickness.

Abstract: There is provided a method of manufacturing a semiconductor device including: preparing a semiconductor substrate having an active region; forming a dielectric layer for gate insulation on the active region; forming a curing layer with a material containing germanium (Ge) on the dielectric layer; heat-treating the curing layer; and removing the curing layer. The germanium-containing material may be silicon germanium (SiGe) or germanium (Ge).

Abstract: A semiconductor device includes a substrate including an NMOS region, a fin active region protruding from the substrate in the NMOS region, the fin active region including an upper surface and a sidewall, a gate dielectric layer on the upper surface and the sidewall of the fin active region, a first metal gate electrode on the gate dielectric layer, the first metal gate electrode having a first thickness at the upper surface of the fin active region and a second thickness at the sidewall of the fin active region, and a second metal gate electrode on the first metal gate electrode, the second metal gate electrode having a third thickness at the upper surface of the fin active region and a fourth thickness at the sidewall of the fin active region, wherein the third thickness is less than the fourth thickness.

Abstract: A semiconductor device having a semiconductor substrate including a first region and a second region is provided. The semiconductor device further includes a gate electrode on the first region and having a first sidewall and a second sidewall, a first source region in the first region proximate to the first sidewall, a first drain region in the first region proximate to the second sidewall, an upper electrode on the second region and having a first sidewall and a second sidewall, a second source region in the second region proximate to the first sidewall of the upper electrode, and a second drain region in the second region proximate to the second sidewall of the upper electrode, wherein an impurity doping concentration of the first source region and the first drain region is greater than an impurity doping concentration of the second source region and the second drain region.

Abstract: A semiconductor device having a semiconductor substrate including a first region and a second region is provided. The semiconductor device further includes a gate electrode on the first region and having a first sidewall and a second sidewall, a first source region in the first region proximate to the first sidewall, a first drain region in the first region proximate to the second sidewall, an upper electrode on the second region and having a first sidewall and a second sidewall, a second source region in the second region proximate to the first sidewall of the upper electrode, and a second drain region in the second region proximate to the second sidewall of the upper electrode, wherein an impurity doping concentration of the first source region and the first drain region is greater than an impurity doping concentration of the second source region and the second drain region.

Abstract: In an embodiment, a method of fabricating a dual gate electrode includes forming an initial semiconductor layer doped with impurities of a first conductivity type on a semiconductor substrate having a first region and a second region. The initial semiconductor layer of the second region is partially etched to form a recessed semiconductor layer that is thinner than the initial semiconductor layer. Impurities of a second conductivity type different from the first conductivity type are implanted into the recessed semiconductor layer to define a first semiconductor layer in the first region and a second semiconductor layer in the second region, respectively. Then, the first and second semiconductor layers are annealed, and the annealed first semiconductor layer is planarized. The resulting structure may be etched to form gate electrodes that are capable of having high concentrations of impurities.

Abstract: In an embodiment, a method of fabricating a dual gate electrode includes forming an initial semiconductor layer doped with impurities of a first conductivity type on a semiconductor substrate having a first region and a second region. The initial semiconductor layer of the second region is partially etched to form a recessed semiconductor layer that is thinner than the initial semiconductor layer. Impurities of a second conductivity type different from the first conductivity type are implanted into the recessed semiconductor layer to define a first semiconductor layer in the first region and a second semiconductor layer in the second region, respectively. Then, the first and second semiconductor layers are annealed, and the annealed first semiconductor layer is planarized. The resulting structure may be etched to form gate electrodes that are capable of having high concentrations of impurities.