Abstract: A semiconductor memory device includes a plurality of banks, each including a plurality of first memory cells and a plurality of second memory cells, a first input/output unit configured to transfer first data between the first memory cells and a plurality of first data pads; a second input/output unit configured to transfer second data between the second memory cells and a plurality of second data pads, a path selection unit configured to transfer the first data, which are input through the first data pads, to both the first and second memory cells, during a test mode, and a test mode control unit configured to compare the first data of the first and second memory cells, and to control at least one of the first data pads to denote a fail status based on a comparison result, during the test mode.

Abstract: A semiconductor memory device includes a plurality of banks, each including a plurality of first memory cells and a plurality of second memory cells, a first input/output unit configured to transfer first data between the first memory cells and a plurality of first data pads, a second input/output unit configured to transfer second data between the second memory cells and a plurality of second data pads, a path selection unit configured to transfer the first data which are input through the first data pads, to both the first and second memory cells, during a test mode, and a test mode control unit configured to compare the first data of the first and second memory cells, and to control the first data pads to denote a fail status based on a comparison result, during the test mode.

Abstract: A semiconductor memory device that can minimize the area of a circuit for generating a BLEQ signal by using one power source voltage terminal floated for the generation of a BLEQ signal. The semiconductor memory device includes a power source supplier configured to supply a power source of a main power source voltage terminal to a sub-power source voltage terminal in response to a mat selection signal for selecting a corresponding memory cell mat among a plurality of memory cell mats, a bit line equalization (BLEQ) signal generator configured to be coupled with the sub-power source voltage terminal and generate a BLEQ signal corresponding to a voltage level of the sub-power source voltage terminal in response to a BLEQ control signal, and a bit line equalizer configured to precharge and equalize a bit line pair in response to the BLEQ signal.

Abstract: A semiconductor memory device includes a plurality of banks, each including a plurality of first memory cells and a plurality of second memory cells; a first input/output unit configured to transfer first data between the first memory cells and a plurality of first data pads; a second input/output unit configured to transfer second data between the second memory cells and a plurality of second data pads; a path selection unit configured to transfer the first data, which are input through the first data pads, to both the first and second memory cells during a test mode; and a test mode control unit configured to compare the first data of the first and second memory cells, and to control at least one of the first data pads to denote a fail status based on a comparison result, during the test mode.

Abstract: A semiconductor memory device includes a plurality of banks, each including a plurality of first memory cells and a plurality of second memory cells, a first input/output unit configured to transfer first data between the first memory cells and a plurality of first data pads, a second input/output unit configured to transfer second data between the second memory cells and a plurality of second data pads, a path selection unit configured to transfer the first data which are input through the first data pads, to both the first and second memory cells, during a test mode, and a test mode control unit configured to compare the first data of the first and second memory cells, and to control the first data pads to denote a fail status based on a comparison result, during the test mode.

Abstract: A semiconductor memory device that can minimize the area of a circuit for generating a BLEQ signal by using one power source voltage terminal floated for the generation of a BLEQ signal. The semiconductor memory device includes a power source supplier configured to supply a power source of a main power source voltage terminal to a sub-power source voltage terminal in response to a mat selection signal for selecting a corresponding memory cell mat among a plurality of memory cell mats, a bit line equalization (BLEQ) signal generator configured to be coupled with the sub-power source voltage terminal and generate a BLEQ signal corresponding to a voltage level of the sub-power source voltage terminal in response to a BLEQ control signal, and a bit line equalizer configured to precharge and equalize a bit line pair in response to the BLEQ signal.

Abstract: Circuit and method for a gate control output circuit having reduced voltage stress on the devices is disclosed. In a circuit of MOS transistors for supplying an output to control a transfer gate, the output having a high voltage level that exceeds a supply voltage, first and second clamping circuits are provided. The first clamping circuit ensures a voltage between the gate and the source/drain and drain/source of a PMOS transistor that couples a pumped voltage to the output does not exceed a predetermined voltage. The second clamping circuit ensures that the voltage between the gate of an NMOS transistor and the output which is coupled to the drain/source of the NMOS transistor does not exceed a predetermined amount. The clamping circuits prevent gate stress problems on the transistors by ensuring the voltages between the gates and the source/drain and drain/source terminals do not exceed predetermined voltages.

Abstract: Disclosed is a timing control circuit for semiconductor device capable of controlling timing of internal signal after packaging by using a fuse. The disclosed comprises: a signal delay unit comprising delay elements and for delaying externally received signal for a predetermined time and outputting the result; and a fuse unit capable of determining whether to enable or disable after packaging the semiconductor device and then, determining whether to delay the signal by the delay element or not according to whether it is enabled or not, thereby controlling delay time of signal by the signal delay unit.

Abstract: A semiconductor memory device for performing a dependent bank operation comprises a plurality of banks consisting of memory cells; a plurality of address latch circuits, shared by two adjacent banks respectively, for receiving global address signals and latching local address signals of the selected bank; and a plurality of control circuits, shared by two adjacent banks respectively, for generating control signals and determining the specific bank that is to be activated.

Abstract: Disclosed is a cell data protection circuit in a semiconductor memory device and a method of driving a refresh mode in the same. The method includes the steps of disabling a word line in a refresh mode faster than in a normal mode, and initiating a bit line equalizing using a same way of the normal mode, wherein the bit line equalizing is initiated after the word line is completely closed so as to prevent an influence of the bit line equalizing on cell data.

Abstract: Disclosed is a timing control circuit for semiconductor device capable of controlling timing of internal signal after packaging by using a fuse. The disclosed comprises: a signal delay unit comprising delay elements and for delaying externally received signal for a predetermined time and outputting the result; and a fuse unit capable of determining whether to enable or disable after packaging the semiconductor device and then, determining whether to delay the signal by the delay element or not according to whether it is enabled or not, thereby controlling delay time of signal by the signal delay unit.

Abstract: Disclosed is a cell data protection circuit in a semiconductor memory device and a method of driving a refresh mode in the same. The method includes the steps of disabling a word line in a refresh mode faster than in a normal mode, and initiating a bit line equalizing using a same way of the normal mode, wherein the bit line equalizing is initiated after the word line is completely closed so as to prevent an influence of the bit line equalizing on cell data.

Abstract: A semiconductor memory device for performing a dependent bank operation comprises a plurality of banks consisting of memory cells; a plurality of address latch circuits, shared by two adjacent banks respectively, for receiving global address signals and latching local address signals of the selected bank; and a plurality of control circuits, shared by two adjacent banks respectively, for generating control signals and determining the specific bank that is to be activated.

Abstract: The present invention related to a semiconductor memory that prevents malfunctions by simplifying input paths of an address decoder and by controlling an output timing of a decoded internal address signal. The present invention includes an address signal generator producing complementary signals. An external address is inputted to the address signal generator by a first control signal and is latched by a second control signal. A decoder generates an internal address by receiving one of the complementary address signals and by decoding the address signal and its inverted signal.

Abstract: A semiconductor memory array for improving packaging reliability and device speed is disclosed in the present invention. The semiconductor memory array includes a peripheral device region in a center portion of the array, a plurality of memory mat regions enclosing the peripheral device region, a pad region formed in the peripheral device region, a plurality of array control regions between the memory mat regions, each array control region horizontally adjacent to a memory mat region, and a plurality of main amplifier regions disposed between the memory mat regions and the peripheral device region.

Abstract: A semiconductor memory includes a control signal generator for generating a first control signal, a second control signal, and a third control signal; a first inverter for receiving an external address in accordance with the first control signal; a latch enabled by the second control signal and latching an output of the first inverter; and an address signal generator enabled by the third control signal, the address signal generator generating complementary address signals by using outputs of the first inverter and the latch.

Abstract: A sense amplifier control circuit in a semiconductor memory supplies a sense amplifier with two power source voltages with voltage levels different from each other, successively. A first logic gate is supplied with a pair of sense amplifier enabling bar signals which are applied to the first logic gate in order. The first logic gate generates a signal of logic value 0 when at least one of the sense amplifier enabling bar signals has logic value 1. A second logic gate generates a first NMOS sense amplifier enabling bar signal of high level when an output of the first logic gate has logic value 0 and a sense amplifier enabling bar signal has logic value 1. A third logic gate generates a first PMOS sense amplifier enabling bar signal of high level when at least one of an output of the first logic gate and a sense amplifier enabling bar signal has logic value 1. A fourth logic gate generates a signal of logic value 1 when at least one of a plurality of MAT selection bar signals has logic value 0.

Abstract: An address signal storage circuit of a data repair controller is disclosed including: a level stabilizer for stabilizing a level of an input signal to a constant level by a level control signal applied from the exterior according to the connection and disconnection of a fuse; a control signal generator for generating first and second control signals by a signal stabilized from the level stabilizer; and a signal storage portion for generating either a signal of a constant level by the first control signal generated from the control signal generator after disabled by a driving control signal applied from the exterior, or an inversion signal of the signal generated when disabled by storing an address signal of a prescribed level by the first and second control signals after enabled by the driving control signal.

Abstract: An output buffer circuit comprising a pull-up transistor, a pull-down transistor coupled to the pull-up transistor, a first voltage source for supplying a driving voltage, a second voltage source for supplying a reference voltage, a device for comparing the driving voltage with the reference voltage, a driving voltage detector for producing a signal in response to operation of the comparing device, first and second pull-up driving buffers, the first and second pull-up driving buffers being activated according to the signal from the driving voltage detector, the pull-up transistor being driven by one of the pull-up driving buffers, and first and second pull-down driving buffers, the first and second pull-down driving buffers being activated according to the signal from the driving voltage detector, and the pull-down transistor being driven by one of the pull-down driving buffers.

Abstract: A circuit for generating a switching control signal which is capable of selectively connecting an internal voltage in the read mode with respect to the driving voltage of a driver and connecting an external voltage in the write mode. The circuit includes a Y-decoder for decoding a Y-address, a Y-driver driven by an internal voltage or an external voltage for outputting a switching control signal, a first switching means controlled by a read enabling bar signal and applying or blocking the internal voltage to/from the Y-driver, and a second switching means controlled by the write enabling signal for applying or blocking the external voltage to/from the Y-driver.