Abstract: A semiconductor memory device includes a lower peripheral circuit structure, an upper peripheral circuit structure, a memory cell structure, which overlap each other in a vertical direction, and a plurality of vertical through-electrodes configured to electrically connect the lower peripheral circuit structure to the upper peripheral circuit structure. The memory cell structure includes a plurality of word lines, a plurality of bit lines, and a plurality of selectors arranged between the plurality of word lines and the plurality of bit lines to constitute a plurality of memory cells. The lower peripheral circuit structure includes a lower semiconductor substrate and a plurality of lower transistors arranged on the lower semiconductor substrate, and the upper peripheral circuit structure includes an upper semiconductor substrate and a plurality of upper transistors arranged on the upper semiconductor substrate.

Abstract: Provided are a multi-layered magnetic thin film stack, a magnetic tunneling junction, and a data storage device. The multi-layered magnetic thin film stack includes a FePd alloy layer including an alloy of iron (Fe) and palladium (Pd); a tunneling barrier layer, which includes MgO and is disposed on the FePd alloy layer; and a Heusler alloy layer disposed between the FePd alloy layer and the tunneling barrier layer, wherein the FePd alloy layer and the Heusler alloy layer constitute a hybrid magnetic layer.

Abstract: Provided are a multi-layered magnetic thin film stack, a magnetic tunneling junction, and a data storage device. The multi-layered magnetic thin film stack includes a FePd alloy layer including an alloy of iron (Fe) and palladium (Pd); a tunneling barrier layer, which includes MgO and is disposed on the FePd alloy layer; and a Heusler alloy layer disposed between the FePd alloy layer and the tunneling barrier layer, wherein the FePd alloy layer and the Heusler alloy layer constitute a hybrid magnetic layer.