Patents by Inventor Taejin BAE

Taejin BAE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260271279
    Abstract: A semiconductor device according to an embodiment includes a first structure including a first substrate, wherein the first substrate includes a memory cell region and a first peripheral circuit region; a second structure overlapping the first structure in a vertical direction and including a second substrate, wherein the second substrate includes a core circuit region and a second peripheral circuit region; and peripheral through-vias penetrating the second substrate in the vertical direction and electrically connected to the first structure. The first peripheral circuit region includes peripheral active patterns, a peripheral bit line extending in the vertical direction and contacting the peripheral active patterns; peripheral gate electrodes overlapping the peripheral active patterns in the vertical direction; and a peripheral interconnection structure electrically connected to at least one of the peripheral bit line or the peripheral gate electrodes.
    Type: Application
    Filed: March 3, 2026
    Publication date: September 10, 2026
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Taejin BAE, Jinwoo HAN
  • Publication number: 20260164673
    Abstract: A semiconductor memory device includes a lower peripheral circuit structure, an upper peripheral circuit structure, a memory cell structure, which overlap each other in a vertical direction, and a plurality of vertical through-electrodes configured to electrically connect the lower peripheral circuit structure to the upper peripheral circuit structure. The memory cell structure includes a plurality of word lines, a plurality of bit lines, and a plurality of selectors arranged between the plurality of word lines and the plurality of bit lines to constitute a plurality of memory cells. The lower peripheral circuit structure includes a lower semiconductor substrate and a plurality of lower transistors arranged on the lower semiconductor substrate, and the upper peripheral circuit structure includes an upper semiconductor substrate and a plurality of upper transistors arranged on the upper semiconductor substrate.
    Type: Application
    Filed: November 7, 2025
    Publication date: June 11, 2026
    Inventors: Taejin BAE, Ilmok PARK
  • Patent number: 10164172
    Abstract: Provided are a multi-layered magnetic thin film stack, a magnetic tunneling junction, and a data storage device. The multi-layered magnetic thin film stack includes a FePd alloy layer including an alloy of iron (Fe) and palladium (Pd); a tunneling barrier layer, which includes MgO and is disposed on the FePd alloy layer; and a Heusler alloy layer disposed between the FePd alloy layer and the tunneling barrier layer, wherein the FePd alloy layer and the Heusler alloy layer constitute a hybrid magnetic layer.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: December 25, 2018
    Assignees: SK HYNIX INC., INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Jongill Hong, Taejin Bae, Sung Joon Yoon
  • Publication number: 20170294574
    Abstract: Provided are a multi-layered magnetic thin film stack, a magnetic tunneling junction, and a data storage device. The multi-layered magnetic thin film stack includes a FePd alloy layer including an alloy of iron (Fe) and palladium (Pd); a tunneling barrier layer, which includes MgO and is disposed on the FePd alloy layer; and a Heusler alloy layer disposed between the FePd alloy layer and the tunneling barrier layer, wherein the FePd alloy layer and the Heusler alloy layer constitute a hybrid magnetic layer.
    Type: Application
    Filed: April 12, 2017
    Publication date: October 12, 2017
    Inventors: Jongill HONG, Taejin BAE, Sung Joon YOON