Abstract: An embodiment voltage converter includes a DC-DC converter and a controller. The DC-DC converter includes a transformer, a main switch connected to an input terminal and the transformer, and first and second synchronous rectification switches connected to an output terminal and the transformer, and the controller is configured to switch the main switch so that the DC-DC converter adjusts a voltage of the input terminal and outputs the voltage to the output terminal and to complementarily switch the first and second synchronous rectification switches without dead time.

Abstract: Provided are a system for business process automation and a method thereof. The system according to some embodiments may include a connect manager configured to register and manage application programming interface (API) information for services, a process execution engine configured to execute a target business process comprising a particular service task, which is a task using a particular service provided by a service module, and a connect broker configured to acquire API information for the particular service, registered through the connect manager, during execution of the target business process in response to a request from the process execution engine, and process the particular service task by sending a request for the particular service to the service module using the acquired API information.

Abstract: An embodiment vehicle includes a DC/DC converter having a first power terminal connected to a first electrode of a first battery, a second power terminal connected to a first electrode of a second battery, and a load terminal connected to a first end of an electric load, and including a switching circuit, a transformer, and a rectifier circuit, and a controller configured to set an operation mode of the DC/DC converter to a low-voltage DC/DC converter (LDC) mode or a state-of-charge (SOC) balancing mode, wherein the DC/DC converter is configured to step down a voltage of the first power terminal through the switching circuit, the transformer, and the rectifier circuit and output the voltage to the load terminal when the LDC mode is performed and to control power transfer between the first and second power terminals through the switching circuit when the SOC balancing mode is performed.

Abstract: A method of supporting decision-making of security control includes: (a) when an system for automatically analyzing a security threat receives a security warning from a security device, collecting security threat events generating the security warning from the security device; (b) when the collected security threat events exceed a preset event processing threshold, generating, by the system for automatically analyzing a security threat, a first request message for preferentially processing a security event; (c) when receiving the first request message generated from the system, determining, by the system for supporting priority of security control, a priority processing order of the security threat events, and notifying the system; and (d) when receiving the second request message generated from the system, determining, by the system for supporting priority of security control, a priority processing order and notifying the system for automatically analyzing a security threat of the determined priority process

Abstract: Disclosed are a system and method for automatically generating a playbook and verifying validity of a playbook based on artificial intelligence, wherein the system present invention includes a system for automatically generating a playbook that automatically generates the playbook, and a system for verifying validity of a playbook that is connected to the system for automatically generating a playbook through a network to perform the verification of the validity on the playbook received from the system for automatically generating a playbook.

Abstract: A device for automatically sorting a cyber attack includes an event feature generator that extracts a unique attacker IP by analyzing attacker IPs for each of the different kinds of security devices, and generates AI learning features of the security events of the different kinds of security devices including feature numerical data quantifying at least two or more features through attack information analysis recorded in the different kinds of security devices based on the information on the security events of the different kinds of security devices mapped to the extracted unique attacker IP, and an attack type sorter that learns the generated feature numerical data using an unsupervised learning algorithm, generates clustering data by sorting the feature numerical data into similar attack data and clustering sorted feature numerical data, and then analyzes the generated clustering data to identify a short-term or long-term attacker's cyber attack type.

Abstract: A capacitor component includes a body having first surface and second surfaces opposing each other and including through-holes penetrating through the first surface and the second surface, a first electrode covering an inner wall of each of the plurality of through-holes, a first common electrode covering the first surface and connected to the first electrode, a dielectric layer surrounded by the first electrode in the through-hole, a second electrode surrounded by the dielectric layer in the through-hole, a second common electrode layer covering the second surface and connected to the second electrode, a first external electrode disposed on at least one of a plurality of side surfaces of the body and connected to the first common electrode layer, and a second external electrode disposed on at least one of the plurality of side surfaces of the body and connected to the second common electrode layer.

Abstract: The present invention relates to an electrode tab welding apparatus for welding electrode tabs of a pouch-shaped battery to each other in a state of gathering the electrode tabs using tab guides in a preliminary welding step of welding the electrode tabs to each other before welding the electrode tabs and an electrode lead of the pouch-shaped battery to each other and an electrode tab welding method using the same.

Abstract: A display device includes a light-emitting device disposed on a substrate and including an emission layer, and a light controller disposed on the light-emitting device. The light controller includes a plurality of main light blocking patterns extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, and a plurality of sub-light blocking patterns disposed between adjacent ones of the plurality of main light blocking patterns, extending in the first direction, and spaced apart from each other in the second direction. Each of the plurality of main light blocking patterns has a first thickness in a thickness direction of the substrate, and each of the plurality of sub-light blocking patterns has a second thickness that is less than the first thickness in the thickness direction of the substrate.

Abstract: A planar transformer and a converter including the same include a first core unit including a first receiving portion extending in a first direction; a second core unit spaced from the first core unit, disposed in parallel with the first core unit in a second direction thereof, and including a second receiving portion extending in the first direction; a first coil unit including a first through hole formed in a center portion thereof and a first coil pattern passing through the first receiving portion and the second receiving portion around the first through hole to form a turn; and a second coil unit including a second through hole formed in a center portion thereof and aligned with the first through hole in a third direction thereof, and a second coil pattern passing through the first receiving portion and the second receiving portion around the second through hole.

Abstract: A method of manufacturing a multilayer metal plate by electroplating includes a first forming operation of forming one of a first metal layer and a second metal layer on a substrate by electroplating, wherein the second metal layer is less recrystallized than the first metal layer, the second metal layer is comprised of nanometer-size grains, and the second metal layer has a higher level of tensile strength than the first metal layer; and a second forming operation of forming, by electroplating, a third metal layer not formed in the first forming operation on a surface of one of the first metal layer and the second metal layer formed in the first forming operation.

Abstract: A semiconductor device includes a plurality of active fins defined by an isolation layer on a substrate, a gate structure on the active fins and the isolation layer, and a gate spacer structure covering a sidewall of the gate structure. A sidewall of the gate structure includes first, second, and third regions having first, second, and third slopes, respectively. The second slope increases from a bottom toward a top of the second region. The second slope has a value at the bottom of the second region less than the first slope. The third slope is greater than the second slope.

Abstract: A semiconductor device includes a plurality of active fins defined by an isolation layer on a substrate, a gate structure on the active fins and the isolation layer, and a gate spacer structure covering a sidewall of the gate structure. A sidewall of the gate structure includes first, second, and third regions having first, second, and third slopes, respectively. The second slope increases from a bottom toward a top of the second region. The second slope has a value at the bottom of the second region less than the first slope. The third slope is greater than the second slope.

Abstract: The present invention relates to a hardware high-speed computation combined RISC-V based computation device for supporting a user-defined instruction set and a method thereof which configures a hardware high-speed computation unit executing a user-defined function through a field programmable gate array (FPGA) in a single chip together with a RISC-V based computation device, executes general computation and user-defined computation in an instruction level, not a separate bus connection configuration, through a program using a RISC-V based instruction set including a user-defined instruction set, and provides flexibility capable of optionally changing the user-defined instruction set and a corresponding function and a method thereof.

Abstract: Semiconductor devices and methods of fabricating the same are provided. The methods of fabricating the semiconductor devices may include providing a substrate including an active pattern protruding from the substrate, forming a first liner layer and a field isolating pattern on the substrate to cover a lower portion of the active pattern, forming a second liner layer on an upper portion of the active pattern and the field isolation pattern, and forming a dummy gate on the second liner layer.

Abstract: The present invention relates to a hardware high-speed computation combined RISC-V based computation device for supporting a user-defined instruction set and a method thereof which configures a hardware high-speed computation unit executing a user-defined function through a field programmable gate array (FPGA) in a single chip together with a RISC-V based computation device, executes general computation and user-defined computation in an instruction level, not a separate bus connection configuration, through a program using a RISC-V based instruction set including a user-defined instruction set, and provides flexibility capable of optionally changing the user-defined instruction set and a corresponding function and a method thereof.

Abstract: A probe includes a probe body for providing an object with a test signal; a tip arranged on an end of the probe body to make contact with the object; and an alignment key protruded from a side of the probe body.

Abstract: A semiconductor device includes a plurality of active fins defined by an isolation layer on a substrate, a gate structure on the active fins and the isolation layer, and a gate spacer structure covering a sidewall of the gate structure. A sidewall of the gate structure includes first, second, and third regions having first, second, and third slopes, respectively. The second slope increases from a bottom toward a top of the second region. The second slope has a value at the bottom of the second region less than the first slope. The third slope is greater than the second slope.

Abstract: Provided are a semiconductor device and a method for fabricating the same. The semiconductor device comprises a first fin type active pattern formed on a substrate and extending in a first direction and including first to third parts. At least one dimension of the third part measuring less than the corresponding dimension of the first part. A gate electrode extending in a second direction different from the first direction is at least partially formed on the first part of the fin type active pattern. A first source/drain is formed on the third part of the fin type active pattern.

Abstract: A semiconductor device includes a plurality of active fins defined by an isolation layer on a substrate, a gate structure on the active fins and the isolation layer, and a gate spacer structure covering a sidewall of the gate structure. A sidewall of the gate structure includes first, second, and third regions having first, second, and third slopes, respectively. The second slope increases from a bottom toward a top of the second region. The second slope has a value at the bottom of the second region less than the first slope. The third slope is greater than the second slope.