Abstract: A semiconductor package including: a first substrate; a first semiconductor chip and a second substrate horizontally spaced apart from each other on the first substrate; and a molding layer on the first substrate, the first semiconductor chip and the second substrate, wherein a thickness of the first semiconductor chip is greater than a thickness of the second substrate, wherein the molding layer exposes a top surface of the second substrate, and wherein the second substrate has fiducial marks exposed on the top surface of the second substrate.

Abstract: Provided is a semiconductor package including a substrate having a first surface, a second surface, and a side surface between the first surface and the second surface, the substrate including an insulating layer and a conductive layer in the insulating layer, a plurality of semiconductor chips on the first surface of the substrate and electrically connected to each other through the conductive layer, a mold on the first surface of the substrate, the side surface of the substrate, and at least a portion of each semiconductor chip of the plurality of semiconductor chips, and a connection bump on the second surface of the substrate and electrically connected to the conductive layer, wherein the conductive layer includes a first metal, and wherein an elastic modulus of the conductive layer is smaller than a first elastic modulus of the first metal.

Abstract: A semiconductor package has a wire bonding structure in which short circuits between wires are prevented and signal integrity (SI) characteristics are improved. The semiconductor package includes a package substrate, a chip stack structure mounted on the package substrate and including at least two semiconductor chips, a bonding wire connecting each of the at least two semiconductor chips to the package substrate, and a sealing material sealing the chip stack structure and the bonding wire on the package substrate. The bonding wire includes a metal wire and a coating layer covering the metal wire and including at least one layer.

Abstract: A semiconductor package includes a substrate including bonding pads, first semiconductor chips stacked on the substrate, first connection members disposed on the substrate and the first semiconductor chips, each first connection member electrically connecting a corresponding first bonding pad to each first semiconductor chip, and connection bumps disposed below the substrate and electrically connected to the bonding pads. Each first semiconductor chip includes first connection pads adjacent to a first edge of the first front surface, a passivation layer disposed on the first front surface, and first trenches disposed in the passivation layer and extending from the first edge of the first front surface toward the first connection pads. Each first trench exposes at least a portion of a corresponding first connection pad.

Abstract: A semiconductor package includes a first semiconductor chip including first chip pads, a second semiconductor chip including second chip pads and stacked on the first semiconductor chip in a vertical direction, wherein the second semiconductor chip exposes a portion of the top surface of the first semiconductor chip, a mold layer covering the first and second semiconductor chips, a redistribution substrate on the mold layer, and a first conductive structure penetrating the mold layer in the vertical direction and electrically connected to a corresponding first chip pad among the plurality of first chip pads. The first conductive structure comprises barrel-shaped sections stacked in the vertical direction. Each barrel-shaped section has a convex circumferential side surface. The first conductive structure contains a first polymer matrix and first metal nanoparticles dispersed within the first polymer matrix.

Abstract: A semiconductor package and a method of manufacturing the same are provided such that the total thickness of a package and the pitch of a chip pad are decreased thereby reducing cracks in wiring. The semiconductor package includes a package substrate, at least two semiconductor chips stacked on the package substrate, in a stepped structure, a side insulation layer disposed on one side surface of each of the at least two semiconductor chips, and a conductive connection pattern disposed on a slope surface of the side insulation layer, a portion of an upper surface of each of the at least two semiconductor chips, and a portion of an upper surface of the package substrate, the conductive connection pattern connecting the at least two semiconductor chips to the package substrate, wherein the conductive connection pattern includes a straight line portion and a bent line portion.

Abstract: A semiconductor package includes a package substrate, a semiconductor chip stack, an interposer and a molding member. The semiconductor chip stack may include a first semiconductor chip on the package substrate and second semiconductor chips stacked on the first semiconductor chip in a vertical direction. End portions in a first horizontal direction of the second semiconductor chips may not be aligned with each other in the vertical direction. The interposer may be disposed between the package substrate and the semiconductor chip stack, and may at least partially overlap the semiconductor chip stack in the first horizontal direction and include a wiring structure. The molding member may be disposed on the package substrate, and may cover the semiconductor chip stack and the interposer. The package substrate may include a hole extending in the vertical direction through a portion of the package substrate between the first semiconductor chip and the interposer.

Abstract: A semiconductor package may include a package substrate including first and second surfaces, which are opposite to each other, a first semiconductor chip on the first surface, a first mold layer on the first surface of the package substrate and top and side surfaces of the first semiconductor chip, a second semiconductor chip and a third semiconductor chip stacked on the second surface, a second mold layer on the second surface of the package substrate, bottom and side surfaces of the second semiconductor chip, and bottom and side surfaces of the third semiconductor chip, a vertical conductive pillar provided to penetrate the second mold layer in a vertical direction and horizontally spaced apart from the second and third semiconductor chips, and connection terminals between a bottom surface of the first semiconductor chip and the first surface. The vertical conductive pillar may be placed on the second surface.

Abstract: A semiconductor package may include a substrate including an upper surface including a first upper pad; first semiconductor chips stacked on the substrate; and a first controller structure in contact with a side surface of at least one of the first semiconductor chips. The first controller structure may include a first controller chip, a first insulating film, and a first conductive film. A first surface of the first controller chip may face a first horizontal direction and may include a first contact pad disposed thereon. The first insulating film may expose the first contact pad and may extend along the first surface of the first controller chip to the substrate. The first conductive film may cover the first contact pad of the first controller chip and the first upper pad of the substrate.

Abstract: A semiconductor package includes a support wiring structure, a semiconductor chip on the support wiring structure, a connection structure on the support wiring structure and spaced apart from the semiconductor chip in a horizontal direction, an interposer including a central portion and an outer portion and having a recess portion provided on a lower surface of the central portion facing the semiconductor chip, wherein the central portion is on the semiconductor chip and the connection structure is connected to the outer portion, and a metal plate disposed along a portion of a surface of the recess portion inside the interposer, wherein the metal plate extends along a side surface of the outer portion of the interposer and the lower surface of the central portion of the interposer, and the metal plate has a cavity passing through a vicinity of a center of the metal plate planarly.

Abstract: A semiconductor package includes a package substrate, a chip stack having first semiconductor chips stacked on the package substrate, a first molding film covering the chip stack on the package substrate, a first connection wire vertically penetrating the first molding film to be connected to the package substrate, and exposed onto an upper surface of the first molding film, a second semiconductor chip disposed on the first molding film, and having a first chip pad disposed on one surface facing the package substrate, a second molding film covering the second semiconductor chip on the first molding film, and a connection terminal connecting the first chip pad and an upper end of the first connection wire.

Abstract: A semiconductor package including a dielectric layer on a substrate and having an opening that partially exposes a top surface of the substrate, a capacitor chip on the substrate and in the opening of the dielectric layer, connection terminals between the substrate and the capacitor chip and connecting the substrate and the capacitor chip to each other, dielectric patches on the substrate and in the opening of the dielectric layer, and an under-fill filling a space between the substrate and the capacitor chip may be provided. The space between the substrate and the capacitor chip includes a first region, a second region, and a third region between the first and second regions. The connection terminals are on the first region and the second region. The dielectric patches are on the third region.

Abstract: A method of manufacturing a semiconductor package may include disposing, in a lower mold, a substrate strip in which a plurality of semiconductor chips are arranged in a horizontal direction, providing, in an upper mold, a release film to which a first encapsulant is attached, allowing the upper mold and the lower mold to be proximate to each other such that a first encapsulant is adjacent to an upper surface of each of the plurality of semiconductor chips, injecting a second encapsulant into a space between the upper mold and the lower mold, heating the first encapsulant and the second encapsulant to form a molded structure including a first encapsulating layer and a second encapsulating layer, allowing the upper mold and the lower mold to be spaced from each other such that the molded structure is separated from the release film, and cutting the molded structure.

Abstract: A semiconductor package including a dielectric layer on a substrate and having an opening that partially exposes a top surface of the substrate, a capacitor chip on the substrate and in the opening of the dielectric layer, connection terminals between the substrate and the capacitor chip and connecting the substrate and the capacitor chip to each other, dielectric patches on the substrate and in the opening of the dielectric layer, and an under-fill filling a space between the substrate and the capacitor chip may be provided. The space between the substrate and the capacitor chip includes a first region, a second region, and a third region between the first and second regions. The connection terminals are on the first region and the second region. The dielectric patches are on the third region.

Abstract: A semiconductor package may include a substrate, a first chip on the substrate, a second chip stacked on and offset from the first chip in a first direction, a third chip stacked on and offset from the second chip in a second direction opposite to the first direction, a first bonding wire connecting the substrate to the first chip, and a second bonding wire connecting the first chip to the third chip. The first chip may include a first chip pad disposed on a top surface of the first chip and spaced apart from the second chip in the second direction. The third chip may include a second chip pad disposed on a bottom surface of the third chip and spaced apart from the second chip in the second direction. The second chip pad may be placed above the first chip pad.

Abstract: A semiconductor package includes; a package substrate, a semiconductor chip on the package substrate, an electromagnetic shield structure on the package substrate and including an upper cover covering an upper surface of the semiconductor chip and a side cover surrounding the semiconductor chip, and a sealing member contacting the semiconductor chip and the electromagnetic shield structure, wherein the side cover includes first through holes and the upper cover includes second through holes.

Abstract: A method of manufacturing a semiconductor package may include providing a substrate having first and second cutting regions respectively provided along first and second side portions opposite to each other and a mounting region between the first and second cutting regions is provided, disposing at least one semiconductor chip on the mounting region, forming a molding member on the substrate, and removing a dummy curl portion and at least portions of dummy runner portions from the molding member. The molding member may include a sealing portion, the dummy curl portion provided outside the second side portion of the substrate, and the plurality of dummy runner portions on the second cutting region to connect the sealing portion and the dummy curl portion. The substrate may include adhesion reducing pads in the second cutting region, which may contact the dummy runner portions respectively.

Abstract: A semiconductor device includes: a semiconductor molding upper mold and a semiconductor molding lower mold, wherein a printed circuit board having a plurality of semiconductor devices mounted thereon is disposed on the semiconductor molding lower mold; and a cavity disposed between the semiconductor molding upper mold and the semiconductor molding lower mold, wherein the printed circuit board includes internal through holes and external through holes, wherein the external through holes are spaced apart from a position where the plurality of semiconductor devices are mounted, and the semiconductor molding lower mold has through holes that overlap the internal through holes and the external through holes.

Abstract: A semiconductor package according to example embodiments may include: a substrate including a connecting portion including a bonding pad; a first semiconductor chip disposed on the substrate; an underfill between the substrate and the first semiconductor chip; a second semiconductor chip disposed on the first semiconductor chip; an encapsulant covering the substrate, the first semiconductor chip, and the second semiconductor chip. The bonding pad is disposed on a level higher than that of an upper pad disposed on an upper surface of the substrate.

Abstract: Provided is a semiconductor device including a tower-shaped or bridge-shaped connection structure and a metal plate. The semiconductor device includes: a package substrate; a semiconductor chip stacked on the package substrate along a vertical direction; a connection structure arranged on the package substrate and formed to surround a sidewall of the semiconductor chip; a metal plate attached to an upper surface of the connection structure; and a sealant formed to cover an upper surface of the semiconductor chip and contact with a side surface of the connection structure.