Abstract: A semiconductor device includes a logic cell region on a substrate, an interconnection layer on the logic cell region, the interconnection layer including a plurality of metal layers on the logic cell region, and a first vertical structure in the interconnection layer, where the first vertical structure vertically connects the logic cell region to an uppermost metal layer of the plurality of metal layers, each of the plurality of unit structures includes a lower via, a lower interconnection line, an upper via, and an upper interconnection line, the lower interconnection line and the upper interconnection line of each respective unit structure of the plurality of unit structures cross each other, and the upper interconnection line of each of the plurality of unit structures includes a first upper interconnection line.

Abstract: A flip-flop circuit may include a selection circuit, a master latch circuit and a slave latch circuit. The selection circuit includes a multiplexer and first and second inverters. The multiplexer outputs a data signal or a scan input signal to a first node in response to an enable signal. The first inverter is connected to the first node and provides an inversion of a signal of the first node to a second node in response to a clock signal. The second inverter is connected to the second node and provides an inversion of the signal of the second node to a third node in response to the clock signal and a signal of a fourth node. The master latch circuit is connected between the third and fourth nodes. The slave latch circuit is connected between the fourth node and an output terminal of the flip-flop circuit.