Patents by Inventor Taek Chang

Taek Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11539294
    Abstract: A multi-level power converter and a method using first, second, third and fourth switching elements, an inductor, and a flying capacitor are presented. A first terminal of the inductor may be connected to a switching terminal connecting the second and third switching elements. A first terminal of the flying capacitor may be connected to a terminal connecting the first and second elements. A second terminal of the flying capacitor may be connected to a terminal connecting the third and fourth switching elements. The multi-level power converter may have a first feedback circuit to generate control signals for setting the switching elements in a plurality of switching states for regulating an output voltage or an output current. The converter may have a second feedback circuit to generate control signals to allow the flying capacitor to be charged or discharged using an inductor current flowing through the inductor.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: December 27, 2022
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Aravind Mangudi, Mark Mercer, James Steele, Taek Chang, Bill McKillop
  • Patent number: 10693372
    Abstract: A multi-level power converter and a method using first, second, third and fourth switching elements, an inductor, and a flying capacitor are presented. A first terminal of the inductor may be connected to a switching terminal connecting the second and third switching elements. A first terminal of the flying capacitor may be connected to a terminal connecting the first and second elements. A second terminal of the flying capacitor may be connected to a terminal connecting the third and fourth switching elements. The multi-level power converter may have a first feedback circuit to generate control signals for setting the switching elements in a plurality of switching states for regulating an output voltage or an output current. The converter may have a second feedback circuit to generate control signals to allow the flying capacitor to be charged or discharged using an inductor current flowing through the inductor.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: June 23, 2020
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Aravind Mangudi, Mark Mercer, James Steele, Taek Chang, Bill McKillop
  • Publication number: 20200044578
    Abstract: A multi-level power converter and a method using first, second, third and fourth switching elements, an inductor, and a flying capacitor are presented. A first terminal of the inductor may be connected to a switching terminal connecting the second and third switching elements. A first terminal of the flying capacitor may be connected to a terminal connecting the first and second elements. A second terminal of the flying capacitor may be connected to a terminal connecting the third and fourth switching elements. The multi-level power converter may have a first feedback circuit to generate control signals for setting the switching elements in a plurality of switching states for regulating an output voltage or an output current. The converter may have a second feedback circuit to generate control signals to allow the flying capacitor to be charged or discharged using an inductor current flowing through the inductor.
    Type: Application
    Filed: July 31, 2018
    Publication date: February 6, 2020
    Inventors: Aravind Mangudi, Mark Mercer, James Steele, Taek Chang, Bill McKillop
  • Patent number: 7362135
    Abstract: A programmable logic fabric includes configurable logic block (CLB) containing registers and combinatorial logic elements. An input switch matrix distributes incoming signals to CLB inputs or inputs of embedded logic elements including a register clock. A routing network allows a variety of routing paths with distinct delays to be selected to route the CLB outputs to the input switch matrices. Presented clock delay insertion architectures allow a leaf node of dedicated clock network and a register clock input can be alternatively routed through the routing network, thereby allowing for the generation of a variable amount of clock delay. Required clock delay for each register minimizing the clock period is computed by clock skew optimization program. A set of alternative clock routes is generated for each register clock where each route delay is close to the corresponding required delay while satisfying the monotone increasing conditions.
    Type: Grant
    Filed: October 4, 2006
    Date of Patent: April 22, 2008
    Inventor: Hyun-Taek Chang