Abstract: An apparatus of tilting a seat cushion of a vehicle, includes a tilting motor, a pinion gear, a sector gear, and a tilting link which perform the tilting operation of the seat cushion and exert a binding force in a tilted state of the seat cushion and are provided to be connected to both of one side and the other side of a seat cushion frame, and has two sector gears positioned on left and right sides and connected to each other by a connection bar so that, by strengthening a binding force of the front portion of the seat cushion, it is possible to secure the safety of passengers in the event of a collision.

Abstract: A method of manufacturing a non-volatile memory device is provided. The method includes forming isolation patterns defining an active region on a substrate, forming a floating gate pattern on the active region, and forming a gate line on the floating gate pattern. The floating gate pattern is self-aligned on the active region and has an impurity ion concentration that becomes relatively low as the floating gate pattern gets nearer to the active region.

Abstract: A method of manufacturing a non-volatile memory device is provided. The method includes forming isolation patterns defining an active region on a substrate, forming a floating gate pattern on the active region, and forming a gate line on the floating gate pattern. The floating gate pattern is self-aligned on the active region and has an impurity ion concentration that becomes relatively low as the floating gate pattern gets nearer to the active region.

Abstract: A method of manufacturing a non-volatile memory device is provided. The method includes forming isolation patterns defining an active region on a substrate, forming a floating gate pattern on the active region, and forming a gate line on the floating gate pattern. The floating gate pattern is self-aligned on the active region and has an impurity ion concentration that becomes relatively low as the floating gate pattern gets nearer to the active region.

Abstract: A method of manufacturing a non-volatile memory device is provided. The method includes forming isolation patterns defining an active region on a substrate, forming a floating gate pattern on the active region, and forming a gate line on the floating gate pattern. The floating gate pattern is self-aligned on the active region and has an impurity ion concentration that becomes relatively low as the floating gate pattern gets nearer to the active region.

Abstract: A semiconductor device includes alignment marks that are aligned with device features. The semiconductor device includes a device feature, a pair of first alignment marks, a pair of second alignment marks, and a pair of third alignment marks. The first alignment marks are aligned along a first direction with the device feature and adjacent to opposite sides of the device feature. The second alignment marks are aligned along a second direction with the device feature that is substantially perpendicular to the first direction, and adjacent to opposite sides of the device feature. The third alignment marks are aligned with the first alignment marks in the first direction and adjacent to opposite sides of the device feature, wherein the third marks are between the first alignment marks and the device feature, and each of the third marks have a shorter length along the first direction than each of the first alignment marks.

Abstract: In a substrate protecting member and a method of forming an analysis sample using the same, the substrate protecting member includes a protective layer attached to a semiconductor substrate to protect a defect portion of the semiconductor substrate and a sensing line including first, second and third conductive lines located on the protective layer. The first conductive line extends in a first direction. The second conductive line extends to an edge of the protective layer in a second direction different from the first direction. The second and third conductive lines are electrically connected to first and second end portions of the first conductive line, respectively. The third conductive line extends to an edge of the protective layer in the second direction.

Abstract: A semiconductor device includes alignment marks that are aligned with device features. The semiconductor device includes a device feature, a pair of first alignment marks, a pair of second alignment marks, and a pair of third alignment marks. The first alignment marks are aligned along a first direction with the device feature and adjacent to opposite sides of the device feature. The second alignment marks are aligned along a second direction with the device feature that is substantially perpendicular to the first direction, and adjacent to opposite sides of the device feature. The third alignment marks are aligned with the first alignment marks in the first direction and adjacent to opposite sides of the device feature, wherein the third marks are between the first alignment marks and the device feature, and each of the third marks have a shorter length along the first direction than each of the first alignment marks.

Abstract: A semiconductor device includes alignment marks that are aligned with device features. The semiconductor device includes a device feature, a pair of first alignment marks, a pair of second alignment marks, and a pair of third alignment marks. The first alignment marks are aligned along a first direction with the device feature and adjacent to opposite sides of the device feature. The second alignment marks are aligned along a second direction with the device feature that is substantially perpendicular to the first direction, and adjacent to opposite sides of the device feature. The third alignment marks are aligned with the first alignment marks in the first direction and adjacent to opposite sides of the device feature, wherein the third marks are between the first alignment marks and the device feature, and each of the third marks have a shorter length along the first direction than each of the first alignment marks.

Abstract: A method of Auger Electron Spectroscopic (AES) analysis for a surface of an insulating sample. The method is characterized by performing an AES analysis after depositing a conductive layer of a designated thickness on the surface of a sample containing an insulating layer by means of an ion beam sputtering for the purpose of the preventing charge accumulation. The conductive layer preferably is deposited to have a thickness of at least 6 .ANG. to 50 .ANG. and a beam voltage used for applying the conductive layer is at least 3 Kev. The conductive layer is made of any of iridium(Ir), chrome(Cr) and gold(Au). Because any electron charge generated on the sample is discharged via the conductive layer, the AES analysis can be performed for a sample containing an insulating layer.

Abstract: Method and apparatus for estimating the performance of a gas tube. The method comprising the steps of: (a) preparing a sample tube to be analyzed and cutting the sample tube in a desired size and shape; (b) examining distribution of defects and surface condition of the cut sample tube with an optical microscope; (c) analyzing structure and composition of surface defects which can not be measured in the step (b), to determine type and composition of the surface defects and shape of a surface grain; (d) analyzing structure of an inner surface-treated layer of the sample tube along the thickness thereof; and (e) synthetically analyzing data for defect density and surface roughness, which are numerically expressed through the steps (a) to (d), to define a reference data which can be used in a semiconductor manufacturing process.