Patents by Inventor Taek-keun Lee

Taek-keun Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8945992
    Abstract: A metal tab die attach paddle (DAP) disposed between the lead frame and a power device die in a power device package reduces the stress exerted on the semiconductor power device die caused by the different coefficients of thermal expansion (CTE) of the semiconductor power device die and the lead frame. In addition the power device package substantially prevents impurities from penetrating into the power device package by increasing the surface creepage distance of a sealant resulting from the metal tab DAP and an optional swaging of the lead frame.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: February 3, 2015
    Assignee: Fairchild Korea Semiconductor, Ltd.
    Inventors: Joon-seo Son, O-seob Jeon, Taek-keun Lee, Byoung-ok Lee
  • Publication number: 20130307145
    Abstract: A semiconductor package including a package substrate; a semiconductor chip on the package substrate; a first via contact on the package substrate; a second via contact on the semiconductor chip; a metal wiring, which is arranged on the first via contact and the second via contact and interconnects the first via contact and the second via contact; a first encapsulating material which is arranged between the metal wiring and the package substrate and encapsulates the semiconductor chip, the first via contact, and the second via contact; and a second encapsulating material which encapsulates the first encapsulating material and the metal wiring.
    Type: Application
    Filed: February 28, 2013
    Publication date: November 21, 2013
    Applicant: FAIRCHILD KOREA SEMICONDUCTOR LTD.
    Inventors: Yoon-jae CHUNG, Yong LIU, Seung-won IM, Byoung-ok LEE, Taek-keun LEE, Joon-seo SON, O-seob JEON
  • Patent number: 8350369
    Abstract: Provided is a high power semiconductor package including: an insulation substrate having first and second surfaces opposite to each other; an interconnection patterns formed on the first surface of the insulation substrate, the interconnection patterns including a plurality of first dimples; a power control semiconductor chip mounted on the first surface of the insulation substrate, the power control semiconductor chip electrically connected with the interconnection patterns; and an encapsulation member encapsulating the insulation substrate, the interconnection patterns, and the power control semiconductor chip and exposing at least a portion of the second surface of the insulation substrate.
    Type: Grant
    Filed: January 4, 2008
    Date of Patent: January 8, 2013
    Assignee: Fairchild Korea Semiconductor, Ltd.
    Inventors: Keun-hyuk Lee, Seung-won Lim, Sung-min Park, Taek-keun Lee
  • Publication number: 20120034741
    Abstract: A metal tab die attach paddle (DAP) disposed between the lead frame and a power device die in a power device package reduces the stress exerted on the semiconductor power device die caused by the different coefficients of thermal expansion (CTE) of the semiconductor power device die and the lead frame. In addition the power device package substantially prevents impurities from penetrating into the power device package by increasing the surface creepage distance of a sealant resulting from the metal tab DAP and an optional swaging of the lead frame.
    Type: Application
    Filed: October 21, 2011
    Publication date: February 9, 2012
    Applicant: Fairchild Korea Semiconductor Co., Ltd.
    Inventors: Joon-seo Son, O-seob Jeon, Taek-keun Lee, Byoung-ok Lee
  • Patent number: 8067826
    Abstract: A metal tab die attach paddle (DAP) disposed between the lead frame and a power device die in a power device package reduces the stress exerted on the semiconductor power device die caused by the different coefficients of thermal expansion (CTE) of the semiconductor power device die and the lead frame. In addition the power device package substantially prevents impurities from penetrating into the power device package by increasing the surface creepage distance of a sealant resulting from the metal tab DAP and an optional swaging of the lead frame.
    Type: Grant
    Filed: January 8, 2008
    Date of Patent: November 29, 2011
    Assignee: Fairchild Korea Semiconductor Ltd.
    Inventors: Joon-Seo Son, O-seob Jeon, Taek-keun Lee, Byoung-ok Lee
  • Publication number: 20080164588
    Abstract: Provided is a high power semiconductor package including: an insulation substrate having first and second surfaces opposite to each other; an interconnection patterns formed on the first surface of the insulation substrate, the interconnection patterns including a plurality of first dimples; a power control semiconductor chip mounted on the first surface of the insulation substrate, the power control semiconductor chip electrically connected with the interconnection patterns; and an encapsulation member encapsulating the insulation substrate, the interconnection patterns, and the power control semiconductor chip and exposing at least a portion of the second surface of the insulation substrate.
    Type: Application
    Filed: January 4, 2008
    Publication date: July 10, 2008
    Applicant: Fairchild Korea Semiconductor, Ltd.
    Inventors: Keun-hyuk Lee, Seung-won Lim, Sung-min Park, Taek-keun Lee
  • Publication number: 20080164589
    Abstract: A metal tab die attach paddle (DAP) disposed between the lead frame and a power device die in a power device package reduces the stress exerted on the semiconductor power device die caused by the different coefficients of thermal expansion (CTE) of the semiconductor power device die and the lead frame. In addition the power device package substantially prevents impurities from penetrating into the power device package by increasing the surface creepage distance of a sealant resulting from the metal tab DAP and an optional swaging of the lead frame.
    Type: Application
    Filed: January 8, 2008
    Publication date: July 10, 2008
    Applicant: Fairchild Korea Semiconductor, Ltd.
    Inventors: Joon-seo Son, O-seob Jeon, Taek-keun Lee, Byoung-ok Lee
  • Publication number: 20040061206
    Abstract: Discrete semiconductor packages are described. The discrete package contains: a lead frame pad which has a first surface and a second surface, wherein the second surface which is the opposite surface of the first surface; leads connected to a side of the lead frame pad; a semiconductor chip attached to the first surface of the lead frame pad; a ceramic layer that directly contacts the second surface of the lead frame pad; and a molding material that entirely encapsulates the lead frame pad, the semiconductor chip, and a portion of the ceramic layer, except for a portion of the leads and the second surface of the ceramic layer. Methods for making such discrete packages are also described.
    Type: Application
    Filed: September 26, 2003
    Publication date: April 1, 2004
    Inventors: Joon-Seo Son, Jong-Hwan Baek, Taek-Keun Lee