Patents by Inventor Taek-Soo Jeon

Taek-Soo Jeon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060226470
    Abstract: A semiconductor device comprising a semiconductor substrate having a first impurity region and a second impurity region, a first gate pattern formed on the first impurity region, and a second gate pattern formed on the second impurity region is disclosed. The first gate pattern comprises a first gate insulation layer pattern, a metal layer pattern having a first thickness, and a first polysilicon layer pattern. The second gate pattern comprises a second gate insulation layer pattern, a metal silicide layer pattern having a second thickness smaller than the first thickness, and a second polysilicon layer pattern. The metal silicide layer pattern is formed from a material substantially the same as the material from which the metal layer pattern is formed. A method for manufacturing the semiconductor device is also disclosed.
    Type: Application
    Filed: April 10, 2006
    Publication date: October 12, 2006
    Inventors: Hag-Ju Cho, Taek-Soo Jeon, Hye-Lan Lee, Sang-Bom Kang, Yu-Gyun Shin
  • Publication number: 20060030097
    Abstract: A method of forming transistor gate structures in an integrated circuit device can include forming a high-k gate insulating layer on a substrate including a first region to include PMOS transistors and a second region to include NMOS transistors. A polysilicon gate layer can be formed on the high-k gate insulating layer in the first and second regions. A metal silicide gate layer can be formed directly on the high-k gate insulating layer in the first region and avoiding forming the metal-silicide in the second region. Related gate structures are also disclosed.
    Type: Application
    Filed: July 18, 2005
    Publication date: February 9, 2006
    Inventors: Taek-Soo Jeon, Yu-Gyun Shin, Sang-Bom Kang, Hong-Bae Park, Hag-Ju Cho, Hye-Lan Lee, Beom-Jun Jin, Seong-Geon Park
  • Patent number: 6930062
    Abstract: A method of forming an oxide layer on a semiconductor substrate includes thermally oxidizing a surface of the substrate to form an oxide layer on the substrate, and then exposing the oxide layer to an ambient including predominantly oxygen radicals to thereby thicken the oxide layer. Related methods of fabricating a recessed gate transistor are also discussed.
    Type: Grant
    Filed: May 21, 2004
    Date of Patent: August 16, 2005
    Assignee: Samsung Electronics Co., Inc.
    Inventors: Sang-Jin Hyun, Yu-Gyun Shin, Bon-Young Koo, Sug-Hun Hong, Taek-Soo Jeon, Jeong-do Ryu
  • Publication number: 20050003679
    Abstract: A method of forming an oxide layer on a semiconductor substrate includes thermally oxidizing a surface of the substrate to form an oxide layer on the substrate, and then exposing the oxide layer to an ambient including predominantly oxygen radicals to thereby thicken the oxide layer. Related methods of fabricating a recessed gate transistor are also discussed.
    Type: Application
    Filed: May 21, 2004
    Publication date: January 6, 2005
    Inventors: Sang-Jin Hyun, Yu-Gyun Shin, Bon-Young Koo, Sug-Hun Hong, Taek-Soo Jeon, Jeong-do Ryu