Abstract: An apparatus of tilting a seat cushion of a vehicle, includes a tilting motor, a pinion gear, a sector gear, and a tilting link which perform the tilting operation of the seat cushion and exert a binding force in a tilted state of the seat cushion and are provided to be connected to both of one side and the other side of a seat cushion frame, and has two sector gears positioned on left and right sides and connected to each other by a connection bar so that, by strengthening a binding force of the front portion of the seat cushion, it is possible to secure the safety of passengers in the event of a collision.

Abstract: A memory device including a substrate, a plurality of channel columns, a gate stack, an interlayer insulating layer, a plurality of first trenches, and at least one second trench. The substrate includes a cell array region and a connection region. The channel columns cross an upper surface of the substrate in the cell array region. The gate stack includes a plurality of gate electrode layers surrounding the channel columns in the cell array region. The gate electrode layers extend to different lengths in the connection region to form a stepped structure. The interlayer insulating layer is on the gate stack. The first trenches divide the gate stack and the interlayer insulating layer into a plurality of regions. The at least one second trench is inside of the interlayer insulating layer in the connection region and between the first trenches.

Abstract: A memory device including a substrate, a plurality of channel columns, a gate stack, an interlayer insulating layer, a plurality of first trenches, and at least one second trench. The substrate includes a cell array region and a connection region. The channel columns cross an upper surface of the substrate in the cell array region. The gate stack includes a plurality of gate electrode layers surrounding the channel columns in the cell array region. The gate electrode layers extend to different lengths in the connection region to form a stepped structure. The interlayer insulating layer is on the gate stack. The first trenches divide the gate stack and the interlayer insulating layer into a plurality of regions. The at least one second trench is inside of the interlayer insulating layer in the connection region and between the first trenches.

Abstract: A memory device including a substrate, a plurality of channel columns, a gate stack, an interlayer insulating layer, a plurality of first trenches, and at least one second trench. The substrate includes a cell array region and a connection region. The channel columns cross an upper surface of the substrate in the cell array region. The gate stack includes a plurality of gate electrode layers surrounding the channel columns in the cell array region. The gate electrode layers extend to different lengths in the connection region to form a stepped structure. The interlayer insulating layer is on the gate stack. The first trenches divide the gate stack and the interlayer insulating layer into a plurality of regions. The at least one second trench is inside of the interlayer insulating layer in the connection region and between the first trenches.

Abstract: A memory device including a substrate, a plurality of channel columns, a gate stack, an interlayer insulating layer, a plurality of first trenches, and at least one second trench. The substrate includes a cell array region and a connection region. The channel columns cross an upper surface of the substrate in the cell array region. The gate stack includes a plurality of gate electrode layers surrounding the channel columns in the cell array region. The gate electrode layers extend to different lengths in the connection region to form a stepped structure. The interlayer insulating layer is on the gate stack. The first trenches divide the gate stack and the interlayer insulating layer into a plurality of regions. The at least one second trench is inside of the interlayer insulating layer in the connection region and between the first trenches.