Patents by Inventor Taek-Sung Kim
Taek-Sung Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9626259Abstract: A user device is provided. The device includes a main power supply, and an auxiliary power supply. The main power supply provides a main power. The auxiliary power supply cuts off the main power according to a power level of the main power supply and provides an auxiliary power upon Sudden Power-Off (SPO).Type: GrantFiled: July 22, 2014Date of Patent: April 18, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Hwan-Jin Yong, Donghyun Song, Janghwan Kim, Young-Goo Ko, Hyuck-Sun Kwon, Taek-Sung Kim, Kwang-Ho Kim, Byungjin Ahn, Dongjin Lee, Byungse So, Jong-Gyu Park, Kyoungsub Oh, Kwan-Jong Park, Jong-Soo Seo, Tae-Hwa Yoo, Min-Ho Kim
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Publication number: 20170018685Abstract: A method of manufacturing a light-emitting diode (LED) includes preparing a substrate, forming a plurality of semiconductor light-emitting units on the substrate, each of the plurality of semiconductor light-emitting units protruding from the substrate and including a first conductive semiconductor layer, and an active layer and a second conductive semiconductor layer, the active layer and the second conductive semiconductor layer sequentially covering the first conductive semiconductor layer, dipping the semiconductor light-emitting units into an aqueous solution containing metal salt and an alkaline ligand compound, and forming an electrode layer on the plurality of semiconductor light-emitting units, wherein the forming the electrode layer includes maintaining a temperature of the aqueous solution between about 40° C. and about 200° C.Type: ApplicationFiled: May 10, 2016Publication date: January 19, 2017Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-hyun CHO, Taek-sung KIM, Nam-goo CHA
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Publication number: 20160370422Abstract: A probing interposer includes a supporting substrate with first and second surfaces facing each other and via patterns penetrating the supporting substrate. Each of the via patterns have a concave portion that is exposed through the first surface and has a shape recessed in a direction from the first surface toward the second surface. The concave portion has a width that is smaller than that of the via pattern, and the width decreases in the direction from the first surface toward the second surface.Type: ApplicationFiled: May 3, 2016Publication date: December 22, 2016Inventors: Taek-Sung Kim, Ji Eon Kim, SoonYong Hur
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Patent number: 9424954Abstract: A semiconductor package includes first and second slave chips stacked vertically; and a master chip connected to the first and second slave chips, each of the slave chips including, a plurality of memory blocks, and a redundancy block, and the master chip including, a fuse block configured to repair a defective memory block detected from the first slave chip and a defective memory block detected from the second slave chip by using the redundancy block of the first slave chip and the redundancy block of the second slave chip, respectively, and a block selection circuit configured to, connect the redundancy blocks of the first and second slave chips, one or more non-defective ones of the plurality of memory blocks of the first slave chip, and one or more non-defective ones of the plurality of memory blocks of the second slave chip to an input/output circuit.Type: GrantFiled: January 8, 2014Date of Patent: August 23, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Taek-Sung Kim, Sangbo Lee, SoonYong Hur
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Patent number: 9372790Abstract: A method is provided for controlling a write operation in a nonvolatile memory device to provide wear leveling, where the nonvolatile memory device includes multiple memory blocks. The method includes reading write indication information with respect to at least a selected memory block of the multiple memory blocks; determining whether a write order of data to be stored in the selected memory block is an ascending order or a descending order, based on the write indication information of the selected memory block; and generating addresses of memory regions in the selected memory block in an ascending order when the write order of the data is determined to be an ascending order, and generating addresses of the memory regions in the selected memory block in a descending order when the write order is determined to be a descending order.Type: GrantFiled: July 30, 2013Date of Patent: June 21, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Wonseok Lee, Youngkug Moon, Taek-Sung Kim
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Publication number: 20150026516Abstract: A user device is provided. The device includes a main power supply, and an auxiliary power supply. The main power supply provides a main power. The auxiliary power supply cuts off the main power according to a power level of the main power supply and provides an auxiliary power upon Sudden Power-Off (SPO).Type: ApplicationFiled: July 22, 2014Publication date: January 22, 2015Inventors: Hwan-Jin YONG, Donghyun SONG, Janghwan KIM, Young-Goo KO, Hyuck-Sun KWON, Taek-Sung KIM, Kwang-Ho KIM, Byungjin AHN, Dongjin LEE, Byungse SO, Jong-Gyu PARK, Kyoungsub OH, Kwan-Jong PARK, Jong-Soo SEO, Tae-Hwa YOO, Min-Ho KIM
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Publication number: 20140347943Abstract: A semiconductor package includes first and second slave chips stacked vertically; and a master chip connected to the first and second slave chips, each of the slave chips including, a plurality of memory blocks, and a redundancy block, and the master chip including, a fuse block configured to repair a defective memory block detected from the first slave chip and a defective memory block detected from the second slave chip by using the redundancy block of the first slave chip and the redundancy block of the second slave chip, respectively, and a block selection circuit configured to, connect the redundancy blocks of the first and second slave chips, one or more non-defective ones of the plurality of memory blocks of the first slave chip, and one or more non-defective ones of the plurality of memory blocks of the second slave chip to an input/output circuit.Type: ApplicationFiled: January 8, 2014Publication date: November 27, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Taek-Sung KIM, Sangbo LEE, SoonYong HUR
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Patent number: 8806271Abstract: A user device is provided. The device includes a main power supply, and an auxiliary power supply. The main power supply provides a main power. The auxiliary power supply cuts off the main power according to a power level of the main power supply and provides an auxiliary power upon Sudden Power-Off (SPO).Type: GrantFiled: December 8, 2009Date of Patent: August 12, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Hwan-jin Yong, Donghyun Song, Janghwan Kim, Young-Goo Ko, Hyuck-Sun Kwon, Taek-Sung Kim, Kwangho Kim, Byungjin Ahn, Dongjin Lee, Byungse So, Jonggyu Park, Kyoungsub Oh, Kwanjong Park, Jongsoo Seo, Taehwa Yoo, Min-ho Kim
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Publication number: 20140040535Abstract: A method is provided for controlling a write operation in a nonvolatile memory device to provide wear leveling, where the nonvolatile memory device includes multiple memory blocks. The method includes reading write indication information with respect to at least a selected memory block of the multiple memory blocks; determining whether a write order of data to be stored in the selected memory block is an ascending order or a descending order, based on the write indication information of the selected memory block; and generating addresses of memory regions in the selected memory block in an ascending order when the write order of the data is determined to be an ascending order, and generating addresses of the memory regions in the selected memory block in a descending order when the write order is determined to be a descending order.Type: ApplicationFiled: July 30, 2013Publication date: February 6, 2014Inventors: WONSEOK LEE, YOUNGKUG MOON, TAEK-SUNG KIM
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Publication number: 20130299771Abstract: A semiconductor device has a semiconductor body including a source region, a channel region, and a drain region, which are sequentially arranged in a longitudinal direction and are doped with the same type of impurity, a gate electrode including metal, and a gate dielectric layer interposed between the semiconductor body and the gate electrode.Type: ApplicationFiled: January 24, 2013Publication date: November 14, 2013Inventors: Sun-pil Youn, Dong-won Kim, Taek-sung Kim
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Patent number: 8254158Abstract: In one embodiment, the semiconductor device includes a non-volatile memory cell array, a write circuit configured to write to the non-volatile memory cell array, and a control circuit. The control circuit is configured to store at least one erase indicator. The erase indicator is associated with at least a portion of the non-volatile memory cell array and indicates a logic state. The control circuit is configured to control the write circuit to write the logic state indicated by the erase indicator in the non-volatile memory cell array during an erase operation of the associated portion of the non-volatile memory cell array.Type: GrantFiled: December 23, 2009Date of Patent: August 28, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Jun Lee, Kwangjin Lee, Taek-Sung Kim, Kwangho Kim, Wooyeong Cho, Hyunho Choi, Hye-Jin Kim, Qi Wang
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Patent number: 8218379Abstract: In one embodiment, the semiconductor device includes a non-volatile memory cell array, a write circuit configured to write to the non-volatile memory cell array, and a control circuit. The control circuit is configured to store at least one erase indicator. The erase indicator is associated with at least a portion of the non-volatile memory cell array and indicates a logic state. The control circuit is configured to control the write circuit to write the logic state indicated by the erase indicator in the non-volatile memory cell array during an erase operation of the associated portion of the non-volatile memory cell array.Type: GrantFiled: December 23, 2008Date of Patent: July 10, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Jun Lee, Kwang-Jin Lee, Taek-Sung Kim, Kwang-Ho Kim, Woo-Yeong Cho, Hyun-Ho Choi, Hye Jin Kim
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Patent number: 8194492Abstract: Disclosed is a semiconductor memory device including a memory cell array having a plurality of variable resistance memory cells divided into first and second areas. An I/O circuit is configured to access the memory cell array under the control of control logic so as to access the first or second area in response to an external command. The I/O circuit accesses the first area using a memory cell unit and the second area using a page unit.Type: GrantFiled: January 25, 2010Date of Patent: June 5, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Qi Wang, Kwang-Jin Lee, Woo-Yeong Cho, Taek-Sung Kim, Kwang-Ho Kim, Hyun-Ho Choi, Yong-Jun Lee, Hye-Jin Kim
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Patent number: 7952956Abstract: A semiconductor memory device includes a memory cell array having a plurality of variable resistance memory cells divided into first and second areas. An I/O circuit is configured to access the memory cell array under the control of control logic so as to access the first or second area in response to an external command. The I/O circuit accesses the first area using a memory cell unit and the second area using a page unit.Type: GrantFiled: April 3, 2009Date of Patent: May 31, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Qi Wang, Kwang-Jin Lee, Woo-Yeong Cho, Taek-Sung Kim, Kwang-Ho Kim, Hyun-Ho Choi
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Publication number: 20100268872Abstract: A data storage system comprising a storage device comprising at least one nonvolatile memory, and a controller connected to the storage device through a channel. The memory controller sends part or all of a command, address and data for a next operation to the nonvolatile memory while the nonvolatile memory device is in a busy state. The memory controller then performs a background operation while the nonvolatile memory device remains in the busy state.Type: ApplicationFiled: April 19, 2010Publication date: October 21, 2010Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong Jin LEE, Taek-Sung KIM, Kwang Ho KIM, Seong Sik HWANG, Hyuck-Sun KWON
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Publication number: 20100146333Abstract: A user device is provided. The device includes a main power supply, and an auxiliary power supply. The main power supply provides a main power. The auxiliary power supply cuts off the main power according to a power level of the main power supply and provides an auxiliary power upon Sudden Power-Off (SPO).Type: ApplicationFiled: December 8, 2009Publication date: June 10, 2010Inventors: Hwan-jin Yong, Donghyun Song, Janghwan Kim, Young-Goo Ko, Hyuck-Sun Kwon, Taek-Sung Kim, Kwangho Kim, Byungjin Ahn, Dongjin Lee, Byungse So, Jonggyu Park, Kyoungsub Oh, Kwanjong Park, Jongsoo Seo, Taehwa Yoo, Mih-ho Kim
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Publication number: 20100124105Abstract: Disclosed is a semiconductor memory device including a memory cell array having a plurality of variable resistance memory cells divided into first and second areas. An I/O circuit is configured to access the memory cell array under the control of control logic so as to access the first or second area in response to an external command. The I/O circuit accesses the first area using a memory cell unit and the second area using a page unit.Type: ApplicationFiled: January 25, 2010Publication date: May 20, 2010Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Qi WANG, Kwang-Jin LEE, Woo-Yeong CHO, Taek-Sung KIM, Kwang-Ho KIM, Hyun-Ho CHOI, Yong-Jun LEE, Hye-Jin KIM
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Publication number: 20100091553Abstract: In one embodiment, the semiconductor device includes a non-volatile memory cell array, a write circuit configured to write to the non-volatile memory cell array, and a control circuit. The control circuit is configured to store at least one erase indicator. The erase indicator is associated with at least a portion of the non-volatile memory cell array and indicates a logic state. The control circuit is configured to control the write circuit to write the logic state indicated by the erase indicator in the non-volatile memory cell array during an erase operation of the associated portion of the non-volatile memory cell array.Type: ApplicationFiled: December 23, 2009Publication date: April 15, 2010Inventors: Yong-Jun Lee, Kwangjin Lee, Taek-Sung Kim, Kwangho Kim, Wooyeong Cho, Hyunho Choi, Hye-Jin Kim, Qi Wang
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Publication number: 20090251954Abstract: Disclosed is a semiconductor memory device including a memory cell array having a plurality of variable resistance memory cells divided into first and second areas. An I/O circuit is configured to access the memory cell array under the control of control logic so as to access the first or second area in response to an external command. The I/O circuit accesses the first area using a memory cell unit and the second area using a page unit.Type: ApplicationFiled: April 3, 2009Publication date: October 8, 2009Applicant: Samsung Electronics Co., Ltd.Inventors: Qi WANG, Kwang-Jin LEE, Woo-Yeong CHO, Taek-Sung KIM, Kwang-Ho KIM, Hyun-Ho CHOI
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Publication number: 20090168494Abstract: In one embodiment, the semiconductor device includes a non-volatile memory cell array, a write circuit configured to write to the non-volatile memory cell array, and a control circuit. The control circuit is configured to store at least one erase indicator. The erase indicator is associated with at least a portion of the non-volatile memory cell array and indicates a logic state. The control circuit is configured to control the write circuit to write the logic state indicated by the erase indicator in the non-volatile memory cell array during an erase operation of the associated portion of the non-volatile memory cell array.Type: ApplicationFiled: December 23, 2008Publication date: July 2, 2009Inventors: Yong-Jun Lee, Kwang-Jin Lee, Taek-Sung Kim, Kwang-Ho Kim, Woo-Yeong Cho, Hyun-Ho Choi, Hye Jin Kim