Abstract: A current generator includes a first current generation circuit configured to generate a first current having a first current noise which depends on a change in a supply voltage, a second current generation circuit configured to generate a second current having a second current noise which depends on the change in the supply voltage, and a current subtracting circuit configured to generate a third current with the first current noise and the second current noise removed by subtracting the second current from the first current.

Abstract: A phase locked loop circuit is provided which includes a bang-bang phase frequency detector configured to receive a reference signal and a feedback signal, detect a phase difference between the reference signal and the feedback signal, output a detection signal on the based on a result of the detection; an analog-digital mixed filter configured to receive the detection signal and output a control signal on the basis of the received detection signal; a voltage controlled oscillator configured to output an output signal in response to the control signal; and a divider configured to divide the output signal by n to output as the feedback signal. The detection signal is a digital signal, and the control signal is an analog signal.

Abstract: A method of operating an all-digital phase-locked loop (ADPLL) includes detecting a phase change in a feedback signal of the ADPLL using a search window and controlling a closed-loop bandwidth of the ADPLL based on a detection result. The closed-loop bandwidth when the phase change is detected outside the search window is greater than the closed-loop bandwidth when the phase change is detected within the search window.

Abstract: A digital phase locked loop (DPLL), a method of operating the same, and a device including the same are provided. The DPLL includes a digitally-controlled oscillator configured to change a frequency and a phase of an output oscillation signal in response to a digital control code; a main divider configured to divide the frequency of the output oscillation signal and generate a first feedback signal based on the divided frequency; and a phase-to-digital converter configured to subdivide the phase of the output oscillation signal and to generate a quantized code by converting a phase difference between a reference signal and the first feedback signal using a phase-subdivided signal resulting from the subdivision. The digital control code is generated based on the quantized code.

Abstract: A multi-phase generator includes an oscillator unit including a plurality of first buffer units forming a single closed loop and a delay unit including a plurality of second buffer units respectively connected to a plurality of nodes, wherein each of the plurality of nodes is connected between two adjacent buffer units of the first buffer units. A phase of an output signal of a second buffer unit, among the second buffer units, lags behind a phase of an output signal of a first buffer unit, among the first buffer units.

Abstract: A method of operating a phase-locked loop (PLL) such as an all-digital PLL includes operations of comparing a reference clock signal with a feedback signal of the PLL and outputting a comparison signal according to a result of the comparison, and detecting whether the PLL is in a lock state by using a number of times the comparison signal is toggled.

Abstract: A multi-phase generator includes an oscillator unit including a plurality of first buffer units forming a single closed loop and a delay unit including a plurality of second buffer units respectively connected to a plurality of nodes, wherein each of the plurality of nodes is connected between two adjacent buffer units of the first buffer units. A phase of an output signal of a second buffer unit, among the second buffer units, lags behind a phase of an output signal of a first buffer unit, among the first buffer units.

Abstract: A method of operating an all-digital phase-locked loop (ADPLL) includes detecting a phase change in a feedback signal of the ADPLL using a search window and controlling a closed-loop bandwidth of the ADPLL based on a detection result. The closed-loop bandwidth when the phase change is detected outside the search window is greater than the closed-loop bandwidth when the phase change is detected within the search window.

Abstract: A current generator includes a first current generation circuit configured to generate a first current having a first current noise which depends on a change in a supply voltage, a second current generation circuit configured to generate a second current having a second current noise which depends on the change in the supply voltage, and a current subtracting circuit configured to generate a third current with the first current noise and the second current noise removed by subtracting the second current from the first current.

Abstract: A method of operating a phase-locked loop (PLL) such as an all-digital PLL includes operations of comparing a reference clock signal with a feedback signal of the PLL and outputting a comparison signal according to a result of the comparison, and detecting whether the PLL is in a lock state by using a number of times the comparison signal is toggled.

Abstract: A digital phase locked loop (DPLL), a method of operating the same, and a device including the same are provided. The DPLL includes a digitally-controlled oscillator configured to change a frequency and a phase of an output oscillation signal in response to a digital control code; a main divider configured to divide the frequency of the output oscillation signal and generate a first feedback signal based on the divided frequency; and a phase-to-digital converter configured to subdivide the phase of the output oscillation signal and to generate a quantized code by converting a phase difference between a reference signal and the first feedback signal using a phase-subdivided signal resulting from the subdivision. The digital control code is generated based on the quantized code.

Abstract: A phase locked loop circuit is provided which includes a bang-bang phase frequency detector configured to receive a reference signal and a feedback signal, detect a phase difference between the reference signal and the feedback signal, output a detection signal on the based on a result of the detection; an analog-digital mixed filter configured to receive the detection signal and output a control signal on the basis of the received detection signal; a voltage controlled oscillator configured to output an output signal in response to the control signal; and a divider configured to divide the output signal by n to output as the feedback signal. The detection signal is a digital signal, and the control signal is an analog signal.

Abstract: A phase locked loop (PLL) circuit and a system including such a PLL that may at least compensate for leakage current in a loop filter. The PLL circuit may include a voltage adjusting unit configured to pump charges based on a phase difference between an oscillation clock signal and a reference clock signal, a loop filter configured to generate a frequency control voltage, a level of which is shifted by the charge pumping of the voltage adjusting unit, a voltage controlled oscillator (VCO) configured to output the oscillation clock signal having a frequency corresponding to the frequency control voltage, and a current control circuit configured to generate a compensation current corresponding to a leakage current generated by the loop filter and allow the compensation current and the leakage current to substantially and/or completely counterbalance each other.

Abstract: A duty correcting circuit includes a duty steerer circuit, a differential clock generator, and a charge pump circuit. The duty steerer circuit corrects a duty cycle of an input clock signal in response to a duty control signal and generates an output clock signal. The differential clock generator generates two internal clock signals having a phase difference of 180° from each other based on the output clock signal. The charge pump circuit performs a charge pump operation in a differential mode in response to the internal clock signals to generate a duty control signal.

Abstract: Provided are a phase locked loop (PLL) circuit, a lock detector employable with a PLL circuit, a system including such a PLL circuit and/or lock detector, and a method of detecting a lock/unlock state of a PLL circuit. The PLL circuit may include a clock generating circuit configured to generate an output clock signal having a predetermined frequency in synchronization with a reference clock signal. The lock detector may be configured to determine that the PLL circuit is in a lock state when a phase difference between the reference clock signal and the output clock signal is equal to or less than a first reference value, determine that the PLL circuit is in an unlock state when the phase difference between the reference clock signal and the output clock signal is greater than a second reference value, and generate a lock detection signal.

Abstract: A duty correcting circuit includes a duty steerer circuit, a differential clock generator, and a charge pump circuit. The duty steerer circuit corrects a duty cycle of an input clock signal in response to a duty control signal and generates an output clock signal. The differential clock generator generates two internal clock signals having a phase difference of 180° from each other based on the output clock signal. The charge pump circuit performs a charge pump operation in a differential mode in response to the internal clock signals to generate a duty control signal.

Abstract: Provided are a phase locked loop (PLL) circuit, a lock detector employable with a PLL circuit, a system including such a PLL circuit and/or lock detector, and a method of detecting a lock/unlock state of a PLL circuit. The PLL circuit may include a clock generating circuit configured to generate an output clock signal having a predetermined frequency in synchronization with a reference clock signal. The lock detector may be configured to determine that the PLL circuit is in a lock state when a phase difference between the reference clock signal and the output clock signal is equal to or less than a first reference value, determine that the PLL circuit is in an unlock state when the phase difference between the reference clock signal and the output clock signal is greater than a second reference value, and generate a lock detection signal.

Abstract: A phase locked loop (PLL) circuit and a system including such a PLL that may at least compensate for leakage current in a loop filter. The PLL circuit may include a voltage adjusting unit configured to pump charges based on a phase difference between an oscillation clock signal and a reference clock signal, a loop filter configured to generate a frequency control voltage, a level of which is shifted by the charge pumping of the voltage adjusting unit, a voltage controlled oscillator (VCO) configured to output the oscillation clock signal having a frequency corresponding to the frequency control voltage, and a current control circuit configured to generate a compensation current corresponding to a leakage current generated by the loop filter and allow the compensation current and the leakage current to substantially and/or completely counterbalance each other.