Abstract: An interface block (11) converts the format of input downstream data (STRM). A CPU (12) receives the format-converted data (DIF) and realizes the MAC function. A TEK process block (13) receives TEK process data (DTEK) obtained from the data (DIF), analyzes the data structure of the TEK process data, and performs decryption processing based on a result of the analysis.

Abstract: The encryption/decryption device includes: a data structure analysis block for receiving encrypted data or data to be encrypted and outputting control data and also the encrypted data or the data to be encrypted as processing block input data; a data control block for determining a mode selection signal according to the control data; and a shared processing block for performing encryption or decryption for the processing block input data and outputting the result. The shared processing block is configured to have the ability to perform encryption and decryption in either of the CBC mode and the CFB mode by performing ECB processing using input key data, and performs encryption or decryption in the mode indicated by the mode selection signal.

Abstract: An interface block (11) converts the format of input downstream data (STRM). A CPU (12) receives the format-converted data (DIF) and realizes the MAC function. A TEK process block (13) receives TEK process data (DTEK) obtained from the data (DIF), analyzes the data structure of the TEK process data, and performs decryption processing based on a result of the analysis.

Abstract: In an error and sync detection circuit, 7-bit byte data is rearranged by a data rearrangement block into 8-bit byte data where 1 byte is comprised of 8 bits. Thereafter, the 8-bit byte data is consistently used throughout the process, and each of such byte data is stored in a data storage block, which is a RAM. In a parity check block, a sync detection operation and a parity check operation are performed on the byte data from the data rearrangement block and the byte data from the data storage block, which has been delayed by 1496 clocks. Thus, the byte-to-byte conversion process eliminates the need for a parallel-to-serial conversion circuit and a serial-to-parallel conversion circuit. Use of a RAM for storing the byte data eliminates the need for a 1496-stage delay element.

Abstract: The encryption/decryption device includes: a data structure analysis block for receiving encrypted data or data to be encrypted and outputting control data and also the encrypted data or the data to be encrypted as processing block input data; a data control block for determining a mode selection signal according to the control data; and a shared processing block for performing encryption or decryption for the processing block input data and outputting the result. The shared processing block is configured to have the ability to perform encryption and decryption in either of the CBC mode and the CFB mode by performing ECB processing using input key data, and performs encryption or decryption in the mode indicated by the mode selection signal.

Abstract: An interface block (11) converts the format of input downstream data (STRM). A CPU (12) receives the format-converted data (DIF) and realizes the MAC function. A TEK process block (13) receives TEK process data (DTEK) obtained from the data (DIF), analyzes the data structure of the TEK process data, and performs decryption processing based on a result of the analysis.

Abstract: In an error and sync detection circuit, 7-bit byte data is rearranged by a data rearrangement block into 8-bit byte data where 1 byte is comprised of 8 bits. Thereafter, the 8-bit byte data is consistently used throughout the process, and each of such byte data is stored in a data storage block, which is a RAM. In a parity check block, a sync detection operation and a parity check operation are performed on the byte data from the data rearrangement block and the byte data from the data storage block, which has been delayed by 1496 clocks. Thus, the byte-to-byte conversion process eliminates the need for a parallel-to-serial conversion circuit and a serial-to-parallel conversion circuit. Use of a RAM for storing the byte data eliminates the need for a 1496-stage delay element.