Abstract: Provided is a data transmission method including obtaining, from a core network (CN), at least one packet to be transmitted to a user equipment via a first cell group or a second cell group, determining a packet to be transmitted via the second cell group, among the at least one packet, transmitting the determined packet to the user equipment via the second cell group, obtaining packet delivery state information of the first cell group and packet delivery state information of the second cell group, determining whether to retransmit the transmitted packet based on the packet delivery state information of the first cell group and the packet delivery state information of the second cell group, and retransmitting the packet determined to be retransmitted to the user equipment via the first cell group.

Abstract: A method, performed by an electronic device, of controlling a state control parameter for adjusting a state of a network of a base station, using any one of a plurality of models, includes: obtaining information related to the state of the network from the base station, performing simulation on each of the plurality of models based on the obtained information related to the state of the network, selecting any one model from among the plurality of models based on a result of the performed simulation, and transmitting a value of the state control parameter, calculated using the selected any one model, to the base station to update the state control parameter.

Abstract: Disclosed is a method of fabricating a semiconductor device. The method comprises stacking an etching target layer, a first mask layer, an under layer, and a photoresist layer on a substrate, irradiating extreme ultraviolet (EUV) radiation on the photoresist layer to form a photoresist pattern, and performing a nitrogen plasma treatment on the photoresist pattern while using the first mask layer as an etching stop layer, the performing continuing until a top surface of the first mask layer is exposed. During the performing, the under layer is etched to form an under pattern below the photoresist pattern.

Abstract: Example embodiments relate to a semiconductor device. The semiconductor device includes a substrate including an active region extending in a first direction, a plurality of bit lines running across the active region in a second direction crossing the first direction, a first spacer on a sidewall of the bit line, and a storage node contact on the active region between adjacent bit lines. The first spacer includes a first part between the storage node contact and the bit line, a second part between the first part and the storage node contact, and a third part between the first and second parts. A minimum vertical thickness of the first part is greater than a maximum vertical thickness of the third part. The maximum vertical thickness of the third part is greater than a maximum vertical thickness of the second part.

Abstract: Example embodiments relate to a semiconductor device. The semiconductor device includes a substrate including an active region extending in a first direction, a plurality of bit lines running across the active region in a second direction crossing the first direction, a first spacer on a sidewall of the bit line, and a storage node contact on the active region between adjacent bit lines. The first spacer includes a first part between the storage node contact and the bit line, a second part between the first part and the storage node contact, and a third part between the first and second parts. A minimum vertical thickness of the first part is greater than a maximum vertical thickness of the third part. The maximum vertical thickness of the third part is greater than a maximum vertical thickness of the second part.

Abstract: Example embodiments relate to a semiconductor device. The semiconductor device includes a substrate including an active region extending in a first direction, a plurality of bit lines running across the active region in a second direction crossing the first direction, a first spacer on a sidewall of the bit line, and a storage node contact on the active region between adjacent bit lines. The first spacer includes a first part between the storage node contact and the bit line, a second part between the first part and the storage node contact, and a third part between the first and second parts. A minimum vertical thickness of the first part is greater than a maximum vertical thickness of the third part. The maximum vertical thickness of the third part is greater than a maximum vertical thickness of the second part.

Abstract: Disclosed is a method of fabricating a semiconductor device. The method comprises stacking an etching target layer, a first mask layer, an under layer, and a photoresist layer on a substrate, irradiating extreme ultraviolet (EUV) radiation on the photoresist layer to form a photoresist pattern, and performing a nitrogen plasma treatment on the photoresist pattern while using the first mask layer as an etching stop layer, the performing continuing until a top surface of the first mask layer is exposed. During the performing, the under layer is etched to form an under pattern below the photoresist pattern.

Abstract: Example embodiments relate to a method for fabricating a semiconductor device. The method for fabricating a semiconductor device includes stacking on a substrate an etching target layer, a first mask layer, and a photoresist layer, irradiating extreme ultraviolet (EUV) radiation on the photoresist layer to form a photoresist pattern, patterning the first mask layer to form a first mask pattern using the photoresist pattern as an etching mask, and patterning the etching target layer to form a target pattern using the first mask pattern as an etching mask. The first mask layer includes at least one of a silicon layer and a titanium oxide layer.

Abstract: Semiconductor devices and method of manufacturing the same are provided. The devices may include a substrate including a first impurity region and second impurity regions spaced apart from the first impurity region and a conductive line. The conductive line may extend in a first direction and may be electrically connected to the first impurity region. The devices may also include first conductive contacts on a side of the conductive line and arranged in the first direction and first insulation patterns on the side of the conductive line and arranged in the first direction. The first conductive contacts may be electrically connected to the second impurity regions. The first conductive contacts and the first insulation patterns may be alternately disposed along the first direction. Top surfaces of the first insulation patterns may be lower than a top surface of the conductive line relative to an upper surface of the substrate.

Abstract: Example embodiments relate to a semiconductor device. The semiconductor device includes a substrate including an active region extending in a first direction, a plurality of bit lines running across the active region in a second direction crossing the first direction, a first spacer on a sidewall of the bit line, and a storage node contact on the active region between adjacent bit lines. The first spacer includes a first part between the storage node contact and the bit line, a second part between the first part and the storage node contact, and a third part between the first and second parts. A minimum vertical thickness of the first part is greater than a maximum vertical thickness of the third part. The maximum vertical thickness of the third part is greater than a maximum vertical thickness of the second part.

Abstract: Example embodiments relate to a semiconductor device. The semiconductor device includes a substrate including an active region extending in a first direction, a plurality of bit lines running across the active region in a second direction crossing the first direction, a first spacer on a sidewall of the bit line, and a storage node contact on the active region between adjacent bit lines. The first spacer includes a first part between the storage node contact and the bit line, a second part between the first part and the storage node contact, and a third part between the first and second parts. A minimum vertical thickness of the first part is greater than a maximum vertical thickness of the third part. The maximum vertical thickness of the third part is greater than a maximum vertical thickness of the second part.

Abstract: Example embodiments relate to a method for fabricating a semiconductor device. The method for fabricating a semiconductor device includes stacking on a substrate an etching target layer, a first mask layer, and a photoresist layer, irradiating extreme ultraviolet (EUV) radiation on the photoresist layer to form a photoresist pattern, patterning the first mask layer to form a first mask pattern using the photoresist pattern as an etching mask, and patterning the etching target layer to form a target pattern using the first mask pattern as an etching mask. The first mask layer includes at least one of a silicon layer and a titanium oxide layer.

Abstract: Semiconductor devices and method of manufacturing the same are provided. The devices may include a substrate including a first impurity region and second impurity regions spaced apart from the first impurity region and a conductive line. The conductive line may extend in a first direction and may be electrically connected to the first impurity region. The devices may also include first conductive contacts on a side of the conductive line and arranged in the first direction and first insulation patterns on the side of the conductive line and arranged in the first direction. The first conductive contacts may be electrically connected to the second impurity regions. The first conductive contacts and the first insulation patterns may be alternately disposed along the first direction. Top surfaces of the first insulation patterns may be lower than a top surface of the conductive line relative to an upper surface of the substrate.

Abstract: Example embodiments relate to a semiconductor device. The semiconductor device includes a substrate including an active region extending in a first direction, a plurality of bit lines running across the active region in a second direction crossing the first direction, a first spacer on a sidewall of the bit line, and a storage node contact on the active region between adjacent bit lines. The first spacer includes a first part between the storage node contact and the bit line, a second part between the first part and the storage node contact, and a third part between the first and second parts. A minimum vertical thickness of the first part is greater than a maximum vertical thickness of the third part. The maximum vertical thickness of the third part is greater than a maximum vertical thickness of the second part.