Abstract: A memory system includes a memory device including a memory cell array divided into a plurality of memory banks, and a memory controller that sends read requests or write requests to the memory device for the purpose of inputting data to or outputting data from the memory banks of the memory cell array, respectively, and sends the read requests so as to be separated from the write requests based on a read-write switching point. In a first turn, the memory controller sets a near switching point before the read-write switching point. The memory controller blocks scheduling at least one of first bank requests, between the near switching point and the read-write switching point. The memory controller schedules at least one of second bank requests, which cause state switching of the memory banks, so as to be issued between the near switching point and the read-write switching point.

Abstract: A memory system includes a memory device including a memory cell array divided into a plurality of memory banks, and a memory controller that sends read requests or write requests to the memory device for the purpose of inputting data to or outputting data from the memory banks of the memory cell array, respectively, and sends the read requests so as to be separated from the write requests based on a read-write switching point. In a first turn, the memory controller sets a near switching point before the read-write switching point. The memory controller blocks scheduling at least one of first bank requests, between the near switching point and the read-write switching point. The memory controller schedules at least one of second bank requests, which cause state switching of the memory banks, so as to be issued between the near switching point and the read-write switching point.

Abstract: Provided is a multi-core device. The multi-core device includes: a plurality of cores outputting a test response value by receiving a test pattern value; a majority analyzer outputting a value corresponding to a majority of the test response value by analyzing the test response value; and a determination unit determining a core outputting a test response value different from the value corresponding to the majority among the plurality of cores.

Abstract: Provided is a multi-core device. The multi-core device includes: a plurality of cores outputting a test response value by receiving a test pattern value; a majority analyzer outputting a value corresponding to a majority of the test response value by analyzing the test response value; and a determination unit determining a core outputting a test response value different from the value corresponding to the majority among the plurality of cores.