Abstract: Disclosed are an aluminum-coated blank, a manufacturing method thereof, and an apparatus for manufacturing the same. The blank includes two or more aluminum-coated steel sheets connected together by a joint, each of the steel sheets including: a base steel sheet including 0.01-0.5 wt % of carbon, 0.01-1.0 wt % of silicon, 0.5-3.0 wt % of manganese, greater than 0 but not greater than 0.05 wt % of phosphorus, greater than 0 but not greater than 0.01 wt % of sulfur, greater than 0 but not greater than 0.1 wt % of aluminum, greater than 0 but not greater than 0.001 wt % of nitrogen, and the balance of iron and other inevitable impurities; and a coating layer including aluminum and formed on at least one surface of the base steel sheet.

Abstract: A semiconductor device includes a substrate having first and second regions, first fin groups spaced along a first direction on the first region, each of the first fin groups including adjacent first and second fins having longitudinal directions in a second direction intersecting the first direction, and third to fifth fins spaced along a third direction on the second region, the third to fifth fins having longitudinal directions in a fourth direction intersecting the third direction. The third through fifth fins are at a first pitch, the first and second fins are at a second pitch equal to or smaller than the first pitch, each of the first fin groups is at a first group pitch greater than three times the first pitch and smaller than four times the first pitch, and a width of the first and second fins is same as width of the third fin.

Abstract: A semiconductor device includes a substrate having first and second regions, first fin groups spaced along a first direction on the first region, each of the first fin groups including adjacent first and second fins having longitudinal directions in a second direction intersecting the first direction, and third to fifth fins spaced along a third direction on the second region, the third to fifth fins having longitudinal directions in a fourth direction intersecting the third direction. The third through fifth fins are at a first pitch, the first and second fins are at a second pitch equal to or smaller than the first pitch, each of the first fin groups is at a first group pitch greater than three times the first pitch and smaller than four times the first pitch, and a width of the first and second fins is same as width of the third fin.

Abstract: A semiconductor device includes a substrate having first and second regions, first fin groups spaced along a first direction on the first region, each of the first fin groups including adjacent first and second fins having longitudinal directions in a second direction intersecting the first direction, and third to fifth fins spaced along a third direction on the second region, the third to fifth fins having longitudinal directions in a fourth direction intersecting the third direction. The third through fifth fins are at a first pitch, the first and second fins are at a second pitch equal to or smaller than the first pitch, each of the first fin groups is at a first group pitch greater than three times the first pitch and smaller than four times the first pitch, and a width of the first and second fins is same as width of the third fin.

Abstract: A vertical tunnel field effect transistor (VTFET) including a fin structure protruding from a substrate including a source/drain region, an epitaxially-grown source/drain structure on the fin structure, a cap including pillar portions, the pillar portions covering side surfaces of the epitaxially-grown source/drain structure and partially covering side surfaces of a top portion of the fin structure, a gate insulator covering remaining portions of the side surfaces of the fin structure under the pillar portions of the cap, a work function metal gate on the gate insulator, and a separation pattern surrounding a bottom portion of a fin structure such that the work function metal gate is vertically between the cap and the separation pattern, the separation pattern electrically isolating the work function metal gate from the source/drain region, and a method of manufacturing the same may be provided.

Abstract: A semiconductor device includes a substrate having first and second regions, first fin groups spaced along a first direction on the first region, each of the first fin groups including adjacent first and second fins having longitudinal directions in a second direction intersecting the first direction, and third to fifth fins spaced along a third direction on the second region, the third to fifth fins having longitudinal directions in a fourth direction intersecting the third direction. The third through fifth fins are at a first pitch, the first and second fins are at a second pitch equal to or smaller than the first pitch, each of the first fin groups is at a first group pitch greater than three times the first pitch and smaller than four times the first pitch, and a width of the first and second fins is same as width of the third fin.

Abstract: Vertical field-effect transistor (VFET) devices and methods of forming VFET devices are provided. The methods may include forming a channel region that protrudes from an upper surface of a substrate in a vertical direction, forming a gate insulator layer on a side of the channel region, after forming the gate insulator layer, forming a top source/drain on the channel region, and forming a gate electrode on the gate insulator layer.

Abstract: A method of fabricating a gate all around semiconductor device is provided.

Abstract: Vertical field-effect transistor (VFET) devices and methods of forming VFET devices are provided. The methods may include forming a channel region that protrudes from an upper surface of a substrate in a vertical direction, forming a gate insulator layer on a side of the channel region, after forming the gate insulator layer, forming a top source/drain on the channel region, and forming a gate electrode on the gate insulator layer.

Abstract: Methods of forming a semiconductor device may include forming a fin-type active pattern that extends in a first direction on a substrate, the fin-type active pattern including a lower pattern on the substrate and an upper pattern on the lower pattern. A field insulating layer is formed on the substrate, the sidewalls of the fin-type active pattern, and a portion upper pattern protruding further away from the substrate than a top surface of the field insulating layer. A dummy gate pattern that intersects the fin-type active pattern and that extends in a second direction that is different from the first direction is formed. The methods include forming dummy gate spacers on side walls of the dummy gate pattern, forming recesses in the fin-type active pattern on both sides of the dummy gate pattern and forming source and drain regions on both sides of the dummy gate pattern.

Abstract: A vertical tunnel field effect transistor (VTFET) including a fin structure protruding from a substrate including a source/drain region, an epitaxially-grown source/drain structure on the fin structure, a cap including pillar portions, the pillar portions covering side surfaces of the epitaxially-grown source/drain structure and partially covering side surfaces of a top portion of the fin structure, a gate insulator covering remaining portions of the side surfaces of the fin structure under the pillar portions of the cap, a work function metal gate on the gate insulator, and a separation pattern surrounding a bottom portion of a fin structure such that the work function metal gate is vertically between the cap and the separation pattern, the separation pattern electrically isolating the work function metal gate from the source/drain region, and a method of manufacturing the same may be provided.

Abstract: A vertical tunnel field effect transistor (VTFET) including a fin structure protruding from a substrate including a source/drain region, an epitaxially-grown source/drain structure on the fin structure, a cap including pillar portions, the pillar portions covering side surfaces of the epitaxially-grown source/drain structure and partially covering side surfaces of a top portion of the fin structure, a gate insulator covering remaining portions of the side surfaces of the fin structure under the pillar portions of the cap, a work function metal gate on the gate insulator, and a separation pattern surrounding a bottom portion of a fin structure such that the work function metal gate is vertically between the cap and the separation pattern, the separation pattern electrically isolating the work function metal gate from the source/drain region, and a method of manufacturing the same may be provided.

Abstract: A vertical tunnel field effect transistor (VTFET) including a fin structure protruding from a substrate including a source/drain region, an epitaxially-grown source/drain structure on the fin structure, a cap including pillar portions, the pillar portions covering side surfaces of the epitaxially-grown source/drain structure and partially covering side surfaces of a top portion of the fin structure, a gate insulator covering remaining portions of the side surfaces of the fin structure under the pillar portions of the cap, a work function metal gate on the gate insulator, and a separation pattern surrounding a bottom portion of a fin structure such that the work function metal gate is vertically between the cap and the separation pattern, the separation pattern electrically isolating the work function metal gate from the source/drain region, and a method of manufacturing the same may be provided.

Abstract: A method of fabricating a gate all around semiconductor device is provided.

Abstract: An integrated circuit device as provided herein may include a device region and an inter-device isolation region. Within the device region, a fin-type active region may protrude from a substrate, and opposite sidewalls of the fin-type active region may be covered by an inner isolation layer. An outer isolation layer may fill an outer deep trench in the inter-device isolation region. The inner isolation layer may extend away from the device region at an inner sidewall of the outer deep trench and into the inter-device isolation region. There may be multiple fin-type active regions, and trenches therebetween. The outer deep trench and the trenches between the plurality of fin-type active regions may be of different heights. The integrated circuit device and methods of manufacturing described herein may reduce a possibility that various defects or failures may occur due to an unnecessary fin-type active region remaining around the device region.

Abstract: Methods of forming a semiconductor device may include forming a fin-type active pattern that extends in a first direction on a substrate, the fin-type active pattern including a lower pattern on the substrate and an upper pattern on the lower pattern. A field insulating layer is formed on the substrate, the sidewalls of the fin-type active pattern, and a portion upper pattern protruding further away from the substrate than a top surface of the field insulating layer. A dummy gate pattern that intersects the fin-type active pattern and that extends in a second direction that is different from the first direction is formed. The methods include forming dummy gate spacers on side walls of the dummy gate pattern, forming recesses in the fin-type active pattern on both sides of the dummy gate pattern and forming source and drain regions on both sides of the dummy gate pattern.

Abstract: A semiconductor device includes a compound semiconductor layer, where the compound semiconductor layer includes separate fin patterns in separate regions. The separate fin patterns may include different materials. The separate fin patterns may include different dimensions, including one or more of width and height of one or more portions of the fin patterns. The separate fin patterns may include an upper pattern and a lower pattern. The upper pattern and the lower pattern may include different materials. The upper pattern and the lower pattern may include different dimensions. Separate regions may include separate ones of an NMOS or a PMOS. The semiconductor device may include gate electrodes on the compound semiconductor layer. Separate gate electrodes may intersect the separate fin patterns.

Abstract: Methods of forming a semiconductor device may include forming a fin-type active pattern that extends in a first direction on a substrate, the fin-type active pattern including a lower pattern on the substrate and an upper pattern on the lower pattern. A field insulating layer is formed on the substrate, the sidewalls of the fin-type active pattern, and a portion upper pattern protruding further away from the substrate than a top surface of the field insulating layer. A dummy gate pattern that intersects the fin-type active pattern and that extends in a second direction that is different from the first direction is formed. The methods include forming dummy gate spacers on side walls of the dummy gate pattern, forming recesses in the fin-type active pattern on both sides of the dummy gate pattern and forming source and drain regions on both sides of the dummy gate pattern.

Abstract: An integrated circuit device as provided herein may include a device region and an inter-device isolation region. Within the device region, a fin-type active region may protrude from a substrate, and opposite sidewalls of the fin-type active region may be covered by an inner isolation layer. An outer isolation layer may fill an outer deep trench in the inter-device isolation region. The inner isolation layer may extend away from the device region at an inner sidewall of the outer deep trench and into the inter-device isolation region. There may be multiple fin-type active regions, and trenches therebetween. The outer deep trench and the trenches between the plurality of fin-type active regions may be of different heights. The integrated circuit device and methods of manufacturing described herein may reduce a possibility that various defects or failures may occur due to an unnecessary fin-type active region remaining around the device region.

Abstract: Example embodiments relate to a metal-oxide semiconductor field effect transistor (MOSFET) of a high performance operating with a necessary threshold voltage while including a channel region formed based on a group III-V compound, and a method of manufacturing the MOSFET. The MOSFET includes a substrate, a semiconductor layer including a group III-V compound on the substrate, and a gate structure disposed on the semiconductor layer, and including a gate electrode formed based on metal and undergone an ion implantation process.