Patents by Inventor Taguhi Yeghoyan

Taguhi Yeghoyan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230326745
    Abstract: A method for producing a layer covering the first surfaces of a structure and leaving the second surfaces uncovered including a sequence for forming an initial layer by PEALD deposition, the sequence including cycles, each including injections of first and second precursor in a reaction chamber, and plasma formation in the reaction chamber. The cycles are carried out at a temperature Tcycle such that Tcycle ? (Tmin - 20° C.), Tmin being the minimum temperature of a nominal temperature window for a PEALD deposition. The method includes exposing the initial layer to a densification plasma such that the exposure to the ion flow makes the material on the first surfaces more resistant to etching than the material on the second surfaces. The method also includes a selective etching step, such that the initial layer covers the first surfaces of the front face of the structure by leaving the second surfaces uncovered.
    Type: Application
    Filed: June 18, 2021
    Publication date: October 12, 2023
    Inventors: Marceline BONVALOT, Christophe VALLEE, Taguhi YEGHOYAN, Nicolas POSSEME
  • Patent number: 11251265
    Abstract: A support for a semiconductor structure includes a charge-trapping layer on a base substrate. The charge-trapping layer consists of a polycrystalline main layer and, interposed in the main layer or between the main layer and the base substrate, at least one intermediate polycrystalline layer composed of a silicon and carbon alloy or carbon. The intermediate layer has a resistivity greater than 1000 ohm·cm.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: February 15, 2022
    Assignees: Soitec, Centre National de la Recherche Scientifiaue
    Inventors: Christophe Figuet, Oleg Kononchuk, Kassam Alassaad, Gabriel Ferro, Véronique Souliere, Christelle Veytizou, Taguhi Yeghoyan
  • Publication number: 20190058031
    Abstract: A support for a semiconductor structure includes a charge-trapping layer on a base substrate. The charge-trapping layer consists of a polycrystalline main layer and, interposed in the main layer or between the main layer and the base substrate, at least one intermediate polycrystalline layer composed of a silicon and carbon alloy or carbon. The intermediate layer has a resistivity greater than 1000 ohm·cm.
    Type: Application
    Filed: February 23, 2017
    Publication date: February 21, 2019
    Applicants: Soitec, Centre National de la Recherche Scientifique, Universite Claude Bernard Lyon 1, Soitec
    Inventors: Christophe Figuet, Oleg Kononchuk, Kassam Alassaad, Gabriel Ferro, Véronique Souliere, Christelle Veytizou, Taguhi Yeghoyan