Patents by Inventor Tah-Kang Joseph Ting
Tah-Kang Joseph Ting has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11721390Abstract: Voltages loaded onto the bit lines in a first CA section of a memory array can be latched by enabling the BLSA between the first section and a second section adjacent to the first section causing latched voltages to propagate to bit lines in the second section. Voltages propagated to the bit lines in the second section using the latches between the second section and a third section. Voltages can be propagated sequentially from section to subsequent adjacent section until a target location is reached. The scheme can be applied as a method of page-data write access in a memory chip, of which page data can be propagated sequentially from section to subsequent adjacent section until a target location is reached, and then, activating a word line in a section of the memory comprising the target location to write voltages to the memory cells at the target location.Type: GrantFiled: January 5, 2022Date of Patent: August 8, 2023Assignee: Piecemakers Technology, Inc.Inventors: Gyh-Bin Wang, Tah-Kang Joseph Ting, Ming-Hung Wang
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Publication number: 20220130450Abstract: Voltages loaded onto the bit lines in a first CA section of a memory array can be latched by enabling the BLSA between the first section and a second section adjacent to the first section causing latched voltages to propagate to bit lines in the second section. Voltages propagated to the bit lines in the second section using the latches between the second section and a third section. Voltages can be propagated sequentially from section to subsequent adjacent section until a target location is reached. The scheme can be applied as a method of page-data write access in a memory chip, of which page data can be propagated sequentially from section to subsequent adjacent section until a target location is reached, and then, activating a word line in a section of the memory comprising the target location to write voltages to the memory cells at the target location.Type: ApplicationFiled: January 5, 2022Publication date: April 28, 2022Applicant: Piecemakers Technology, Inc.Inventors: Gyh-Bin Wang, Tah-Kang Joseph Ting, Ming-Hung Wang
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Patent number: 11250904Abstract: Voltages loaded onto the bit lines in a first CA section of a memory array can be latched by enabling the BLSA between the first section and a second section adjacent to the first section causing latched voltages to propagate to bit lines in the second section. Voltages propagated to the bit lines in the second section using the latches between the second section and a third section. Voltages can be propagated sequentially from section to subsequent adjacent section until a target location is reached. The scheme can be applied as a method of page-data write access in a memory chip, of which page data can be propagated sequentially from section to subsequent adjacent section until a target location is reached, and then, activating a word line in a section of the memory comprising the target location to write voltages to the memory cells at the target location.Type: GrantFiled: September 30, 2020Date of Patent: February 15, 2022Assignee: Piecemakers Technology, Inc.Inventors: Gyh-Bin Wang, Tah-Kang Joseph Ting, Ming-Hung Wang
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Patent number: 11183231Abstract: An apparatus for enhancing prefetch access in a memory module may include a memory chip. The memory chip includes a memory cell array, a plurality of bit lines and a plurality of word lines, a plurality of BLSAs, and a plurality of main data lines. The memory cell array may be arranged to store data, and the plurality of bit lines and the plurality of word lines may be arranged to perform access control of the memory cell array. The plurality of BLSAs may sense a plurality of bit-line signals restored from the plurality of memory cells and convert the plurality of bit-line signals into a plurality of amplified signals, respectively. The main data lines may directly output the amplified signals, through selection of CSLs of the BLSAs on the memory chip, to a secondary semiconductor chip, for performing further processing of the memory module, thereby enhancing the prefetch access.Type: GrantFiled: June 17, 2020Date of Patent: November 23, 2021Assignee: Piecemakers Technology, Inc.Inventors: Gyh-Bin Wang, Ming-Hung Wang, Tah-Kang Joseph Ting
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Publication number: 20210158856Abstract: An apparatus for enhancing prefetch access in a memory module may include a memory chip. The memory chip includes a memory cell array, a plurality of bit lines and a plurality of word lines, a plurality of BLSAs, and a plurality of main data lines. The memory cell array may be arranged to store data, and the plurality of bit lines and the plurality of word lines may be arranged to perform access control of the memory cell array. The plurality of BLSAs may sense a plurality of bit-line signals restored from the plurality of memory cells and convert the plurality of bit-line signals into a plurality of amplified signals, respectively. The main data lines may directly output the amplified signals, through selection of CSLs of the BLSAs on the memory chip, to a secondary semiconductor chip, for performing further processing of the memory module, thereby enhancing the prefetch access.Type: ApplicationFiled: June 17, 2020Publication date: May 27, 2021Inventors: Gyh-Bin Wang, Ming-Hung Wang, Tah-Kang Joseph Ting
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Patent number: 9997224Abstract: A memory architecture includes K first control lines, M groups of second control lines and a memory cell array. K and M are positive integers. Each group of second control lines includes at least one second control line. The memory cell array includes M memory banks. Each memory bank is coupled to the K first control lines. The M memory banks are selected according to M bank select signals respectively so as to receive a shared set of first control signals through the K first control lines. The M memory banks are coupled to the M groups of second control lines respectively, and receive independent M sets of second control signals through the M groups of second control lines respectively. Each memory bank performs one of a column select operation and a sense amplification operation according to the set of first control signals and a set of second control signals.Type: GrantFiled: January 24, 2017Date of Patent: June 12, 2018Assignee: Piecemakers Technology, Inc.Inventors: Ming-Hung Wang, Gyh-Bin Wang, Tah-Kang Joseph Ting
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Publication number: 20180068700Abstract: A memory architecture includes K first control lines, M groups of second control lines and a memory cell array. K and M are positive integers. Each group of second control lines includes at least one second control line. The memory cell array includes M memory banks. Each memory bank is coupled to the K first control lines. The M memory banks are selected according to M bank select signals respectively so as to receive a shared set of first control signals through the K first control lines. The M memory banks are coupled to the M groups of second control lines respectively, and receive independent M sets of second control signals through the M groups of second control lines respectively. Each memory bank performs one of a column select operation and a sense amplification operation according to the set of first control signals and a set of second control signals.Type: ApplicationFiled: January 24, 2017Publication date: March 8, 2018Inventors: Ming-Hung Wang, Gyh-Bin Wang, Tah-Kang Joseph Ting
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Patent number: 9679622Abstract: A control method of a memory device, a memory device and a memory system are provided. The memory system includes a memory control unit and a memory die. The memory die performs a data access operation asynchronously with respect to a system clock according to address information and an access signal generated from the memory control unit. When operating in a read mode, the memory die generates a data tracking signal according to a memory internal read time which is an elapsed time for data to be read to be read out from the memory die. The memory control unit and the memory die obtain required data according to respective data tracking signals transmitted therebetween. The control method defines an asynchronous memory interface protocol which realizes reliable and high speed data transmission.Type: GrantFiled: April 1, 2015Date of Patent: June 13, 2017Assignee: Piecemakers Technology, Inc.Inventors: Gyh-Bin Wang, Tah-Kang Joseph Ting, Yung-Ching Hsieh
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Patent number: 9653148Abstract: A memory device includes a common data bus, a plurality of memory banks and a control circuit. The memory banks are coupled to the common data bus. The memory banks share the common data bus. Each of the memory banks includes a storage device and a data register. The data register is coupled between the storage device the common data bus, and is arranged for storing data read from the storage device. The control circuit is coupled to storage devices and data registers of the memory banks, and is arranged for referring to an address signal and an access signal to control the storage device of said each memory bank to output the data to the corresponding data register, and referring to the address signal and a programmable latency time to control the data registers to output data from the memory banks to the common data bus.Type: GrantFiled: February 18, 2016Date of Patent: May 16, 2017Assignee: Piecemakers Technology, Inc.Inventors: Tah-Kang Joseph Ting, Gyh-Bin Wang, Ming-Hung Wang
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Patent number: 9466355Abstract: A memory architecture includes K first wordlines, M groups of second wordlines, a memory cell array and M switch circuits. K and M are positive integers. Each group of second wordlines includes a plurality of second wordlines. The memory cell array includes M memory banks. The M memory banks are coupled to the M groups of second wordlines respectively, and receive independent M sets of second wordline signals through the M groups of second wordlines respectively. M switch circuits are disposed in correspondence with the M memory banks respectively. Each switch circuit selectively couples the K first wordlines to a corresponding memory bank so that the corresponding memory bank receives a shared set of first wordline signals through the K first wordline. Each memory bank performs a data access operation according to the received set of first wordline signals and a corresponding set of second wordline signals.Type: GrantFiled: May 14, 2015Date of Patent: October 11, 2016Assignee: Piecemakers Technology, Inc.Inventors: Tah-Kang Joseph Ting, Gyh-Bin Wang
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Publication number: 20150332751Abstract: A memory architecture includes K first wordlines, M groups of second wordlines, a memory cell array and M switch circuits. K and M are positive integers. Each group of second wordlines includes a plurality of second wordlines. The memory cell array includes M memory banks. The M memory banks are coupled to the M groups of second wordlines respectively, and receive independent M sets of second wordline signals through the M groups of second wordlines respectively. M switch circuits are disposed in correspondence with the M memory banks respectively. Each switch circuit selectively couples the K first wordlines to a corresponding memory bank so that the corresponding memory bank receives a shared set of first wordline signals through the K first wordline. Each memory bank performs a data access operation according to the received set of first wordline signals and a corresponding set of second wordline signals.Type: ApplicationFiled: May 14, 2015Publication date: November 19, 2015Inventors: Tah-Kang Joseph Ting, Gyh-Bin Wang
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Publication number: 20150287445Abstract: A control method of a memory device, a memory device and a memory system are provided. The memory system includes a memory control unit and a memory die. The memory die performs a data access operation asynchronously with respect to a system clock according to address information and an access signal generated from the memory control unit. When operating in a read mode, the memory die generates a data tracking signal according to a memory internal read time which is an elapsed time for data to be read to be read out from the memory die. The memory control unit and the memory die obtain required data according to respective data tracking signals transmitted therebetween. The control method defines an asynchronous memory interface protocol which realizes reliable and high speed data transmission.Type: ApplicationFiled: April 1, 2015Publication date: October 8, 2015Inventors: Gyh-Bin Wang, Tah-Kang Joseph Ting, Yung-Ching Hsieh
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Publication number: 20150235678Abstract: An adaptive control method based on an input clock includes: performing a read process according to the input clock; receiving a read command; receiving a data signal via a data line according to the read command; enabling an amplifier element according to at least the input clock; and utilizing the amplifier element to amplify the data signal.Type: ApplicationFiled: February 17, 2015Publication date: August 20, 2015Inventors: Tah-Kang Joseph Ting, Li-Chin Tien
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Patent number: 8520427Abstract: A memory cell comprising a first switch device, a second switch device and a capacitor is disclosed. The first switch device has: a control terminal coupled to a select line, wherein the first switch device is controlled by the select line; a first terminal, coupled to a bit line parallel with the select line. The second switch device has: a first terminal, coupled to the second terminal of the first switch device; a control terminal, coupled to a word line orthogonal to the bit line and the select line, wherein the second switch device is controlled by the word line. The capacitor has a first terminal coupled to the second terminal of the second switch device and a second terminal coupled to a predetermined voltage level, wherein the data is read from the capacitor or written to the capacitor via the bit line.Type: GrantFiled: February 3, 2012Date of Patent: August 27, 2013Assignee: Nanya Technology Corp.Inventor: Tah-Kang Joseph Ting
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Publication number: 20120213028Abstract: A memory cell comprising a first switch device, a second switch device and a capacitor is disclosed. The first switch device has: a control terminal coupled to a select line, wherein the first switch device is controlled by the select line; a first terminal, coupled to a bit line parallel with the select line. The second switch device has: a first terminal, coupled to the second terminal of the first switch device; a control terminal, coupled to a word line orthogonal to the bit line and the select line, wherein the second switch device is controlled by the word line. The capacitor has a first terminal coupled to the second terminal of the second switch device and a second terminal coupled to a predetermined voltage level, wherein the data is read from the capacitor or written to the capacitor via the bit line.Type: ApplicationFiled: February 3, 2012Publication date: August 23, 2012Inventor: Tah-Kang Joseph Ting
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Patent number: 7898319Abstract: A method and apparatus are provided for improving the efficiency in charge pump systems for low power applications. This first embodiment provides a method and apparatus which defines a charge pump output voltage high target which turns off a charge pump enable signal and a charge pump outlet voltage low target which turns on a charge pump enable signal. A second embodiment defines a protection time where the charge pumping continues until a predefined phase is completed and the leakage paths are disabled. A third embodiment defines a phase memory block, which continues or remembers the phase until the next request for charge pumping. This prevents the circuitry from entering a window where charge leakage, which diminishes charge pumping efficiency, could occur.Type: GrantFiled: December 6, 2004Date of Patent: March 1, 2011Assignee: Etron Technology, Inc.Inventors: Jenshou Hsu, Tah-Kang Joseph Ting
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Patent number: 7475305Abstract: A method to optimize a data strobe for a multiple circuit, automatic test system is achieved. The method comprises, first, probing, in parallel, a circuit group wherein the circuit group comprises a plurality of circuits. Next, a data strobe of an automatic test system is initialized to a strobe set point relative to a system clock cycle. Next, the function of each of the circuits is partially tested, in parallel, using the strobe set point. Next, the circuit yield of the circuit group from the step of partially testing at the strobe set point is logged. Next, the data strobe is updated to a new strobe set point. Next, the steps of testing, logging, and updating are repeated until a specified range of strobe set points is completed. Finally, the data strobe is set for the circuit group to the strobe set point associated with the highest circuit yield.Type: GrantFiled: July 5, 2005Date of Patent: January 6, 2009Assignee: Etron Technology, Inc.Inventors: Tah-Kang Joseph Ting, Shih-Hsing Wang, Hong-Jie Chen
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Patent number: 7292494Abstract: A method for a deep power down mode is described for a memory chip in which voltage regulators and charge pumps are turned off, memory cell voltages are floated, and support circuit internal power supply voltages are replaced by voltages that are derived from the external chip voltage. Prior to being placed into a deep power down mode, all memory cells are placed into a precharge state from which the memory cell voltages are floated upon entering the deep power down mode. Pass through circuits connect externally derived voltages to the support circuit power supply voltage lines, controlled by a deep power down signal. Maintaining a voltage bias on the support circuits prevents latch up problems when the memory chip is brought out of the deep power down mode.Type: GrantFiled: January 26, 2006Date of Patent: November 6, 2007Assignee: Etron Technology Inc.Inventors: Jen-Shou Hsu, Tah-Kang Joseph Ting, Ming-Hung Wang, Bor-Doou Rong
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Patent number: 7031219Abstract: A method for a deep power down mode is described for a memory chip in which voltage regulators and charge pumps are turned off, memory cell voltages are floated, and support circuit internal power supply voltages are replaced by voltages that are derived from the external chip voltage. Prior to being placed into a deep power down mode, all memory cells are placed into a precharge state from which the memory cell voltages are floated upon entering the deep power down mode. Pass through circuits connect externally derived voltages to the support circuit power supply voltage lines, controlled by a deep power down signal. Maintaining a voltage bias on the support circuits prevents latch up problems when the memory chip is brought out of the deep power down mode.Type: GrantFiled: June 4, 2004Date of Patent: April 18, 2006Assignee: Etron Technology, Inc.Inventors: Jen-Shoe Hsu, Tah-Kang Joseph Ting, Ming-Hung Wang, Bor-Doou Rong
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Patent number: RE40887Abstract: A new method is provided for the creation of Input/Output connection points to a semiconductor device package. An extension is applied to the conventional I/O connect points of a semiconductor device, allowing the original I/O point location to be relocated to a new point of I/O interconnect that may be in the vicinity of the original point of I/O interconnect but can also be located at a distance from this original point of I/O interconnect. Layers of passivation and polyimide are provided for proper creation and protection of the extended and relocated I/O pads. Wire bonding is used to further interconnect the relocated I/O pads.Type: GrantFiled: July 15, 2005Date of Patent: September 1, 2009Assignees: Megica Corporation, Etron Technology, Inc.Inventors: Mou-Shiung Lin, Tah-Kang Joseph Ting