Abstract: A method and a device for error detection, in particular for error correction, in in-memory computations with a set of memory cells for determining a result of a linear operation. Each respective memory cell in the set of memory cells includes a respective resistance. The device includes the set of memory cells and a memory cell for determining a checksum, that includes a resistance that is the same or essentially the same as the sum of the respective resistances.

Abstract: An analog-to-digital converter device designed to form a digital output signal based on an input current. The analog-to-digital converter device has a first analog-to-digital converter unit of a first type and a second analog-to-digital converter unit of a second type, wherein the first analog-to-digital converter unit is designed to receive the input current and, based on the input current, to form a first portion of the digital output signal and to output a first output current to the second analog-to-digital converter unit, wherein the second analog-to-digital converter unit is designed to form a second portion of the digital output signal based on the first output current.

Abstract: A device including a first input for receiving an input current, a second input for receiving a reference current, and a first output.

Abstract: A method for processing input variables using a processing device having at least a first transistor, for example a field-effect transistor. The method includes: providing the first transistor and a first memristive circuit device which characterizes a first input variable associated with the first transistor, wherein a charging current of a capacitor associated with a control electrode of the first transistor can be influenced by means of the first memristive element; applying to the control electrode of the first transistor a first control signal which characterizes a second input variable associated with the first transistor and which has at least periodically a non-constant amplitude; ascertaining a first output variable on the basis of a first variable characterizing a time curve of a current through a load path of the first transistor.

Abstract: A method for processing input variables, comprising: application of a first input variable to a control electrode of a first transistor; application of a second input variable to a current leakage device, wherein the current leakage device is designed to connect a load path of the first transistor selectively to a first circuit node or a second circuit node based on the second input variable.

Abstract: A method for processing input variables by means of a processing device having least a first transistor. The method including: providing the first transistor and a first memristive element, which characterizes a first input variable associated with the first transistor, wherein a charging current of a capacitance associated with a control electrode of the first transistor can be influenced using the first memristive element; applying to the control electrode of the first transistor a first output variable which characterizes a second input variable associated with the first transistor; ascertaining a first output variable which characterizes at least one product of the first input variable and of the second input variable, based on a first variable characterizing a time profile of a current through a load path of the first transistor.

Abstract: A circuit for carrying out a vector operation. The circuit includes: memory cells, connected to a column line, each having an input terminal and a semiconductor switching element, the gate terminal of which is connected to the input terminal, and the drain or the source terminal being connected to the column line, wherein when a sufficiently high gate voltage is at the gate terminal, the memory cell is activated so that an electrical cell current is conducted out of or into the column line at suitable voltages; an input voltage circuit connected to the input terminals; a detection circuit connected to the column line and having an analog-to-digital converter which determines a digital value corresponding to the intensity of a measurement current flowing into or out of the column line, the detection circuit being configured to detect the digital value determined by the analog-to-digital converter, and reduce the measurement current.

Abstract: A method for processing input variables using a processing device including at least two field-effect transistors. Drain-to-source paths of the at least two field-effect transistors are each connected to a first circuit node. The method includes: applying to a gate electrode of the first field-effect transistor a first drive signal which characterizes a first input variable associated with the first field-effect transistor; applying to a gate electrode of the second field-effect transistor a second drive signal which characterizes a first input variable associated with the second field-effect transistor, wherein at least one of the first drive signal and/or the second drive signal has a non-constant amplitude.

Abstract: The disclosure relates to a method for mapping an input vector to an output vector by means of a matrix circuit which has memory cells arranged in a matrix in a plurality of rows and a plurality of columns and first, second and third lines, each memory cell having an adjustable memory state, is connected to the first line (22) of the corresponding row, is connected to the second and third lines of the corresponding column and is set up to generate an electrical current (I1, I2, I3) depending on the memory state and voltages applied to the first, second and third lines, is connected to the second and third lines of the corresponding column and is arranged to conduct an electric current (I1, I2, I3) into the third line (26) as a function of the memory state and voltages applied to the first, second and third lines, each memory cell having a semiconductor switching element (28) with a control terminal which is connected to the second line (24) of the corresponding column; wherein input voltages (U1, U2, U3) corr

Abstract: A method for operating a memory device comprising at least one memory unit. The at least one memory unit includes a bistable multivibrator and two access transistors for the controllable connection of the bistable multivibrator to two secondary control lines associated with the at least one memory unit. The connection of the bistable multivibrator to the two secondary control lines can be controlled using a first primary control line. The method includes: applying a control signal to a control terminal of at least one of the two access transistors in such a way that a load path of the at least one access transistor is at least partially electrically conductive, with respect to a high-resistance state of the load path of the at least one access transistor; determining a first variable which characterizes at least one current flowing through the load path of the at least one access transistor.

Abstract: A method for approximatively determining at least one scalar product of at least one input vector with a weight vector. Input components of the input vector and weight components of the weight vector are present in binary form. At least one matrix circuit is used, wherein the memory cells are programmed according to bits of the weight components. Bits with the same significance of at least a portion of the weight components are respectively programmed in memory cells of the same column. For each of one or more subsets of the input components, a bit sum determination is carried out. To a corresponding subset of the row lines, voltages are applied according to bits with the same significance of the respective subset of the input components and a limited bit sum is determined as the output value of the respective analog-to-digital converter.

Abstract: An apparatus. The apparatus includes at least a first comparator device, which is designed to compare a first input current with a first reference current and, based on the comparison, to output a first output current to a second comparator device, wherein the first output current corresponds to a difference of the first reference current and the first input current if the first input current is smaller than the first reference current, and wherein the first output current corresponds to a difference of the first input current and the first reference current if the first input current is greater than or equal to the first reference current.

Abstract: An arithmetic unit for calculating an approximate value for a product or a sum of two inputted numbers. The arithmetic unit includes arithmetic modules, at least one of the arithmetic modules being provided to calculate individual products or individual sums of digits of the inputted numbers, and the arithmetic modules being connected in an adder that is designed to calculate digits of the product or of the sum from the individual products or from the individual sums. An arithmetic module that is required for the calculation of at least one individual product or individual sum, and/or is required for the propagation of this individual product or this individual sum onto the product or the sum, being absent in the arithmetic unit or being connected there in such a way that it is capable of being selectively deactivated, completely or partially, for the running time of the arithmetic unit.

Abstract: A memory device comprising a plurality of memory cells situated in a first cell field, multiple first bit lines, each respectively connected to multiple memory cells of the first cell field to enable access to the memory cells via the bit line, and multiple sense amplifier pairs which respectively comprise a first and a second sense amplifier. Each first bit line is assigned to a sense amplifier pair, each first bit line being connected to a respective first semiconductor switch element, through which the bit line is electroconductively connectible to and insulatable from the first sense amplifier of the sense amplifier pair, to which the bit line is assigned. Each first bit line is connected to a respective second semiconductor switch element, through which the bit line is electroconductively connectible to and insulatable from the second sense amplifier of the sense amplifier pair, to which the bit line is assigned.

Abstract: A memory device comprising a cell field having memory cells, N bit lines, which are respectively connected to at least one of the memory cells of the cell field, N being a whole number greater than one, N sense amplifiers; a bit shift circuit, which has S switch element rows, S being a whole number greater than one and a row number in the range from zero to S?1 being assignable to each switch element row. Each switch element row includes at least one semiconductor switch element connected to one of the bit lines and one of the sense amplifiers. Switch elements of each row connect all bit lines, whose bit line number is smaller than or equal to N minus the row number, to sense amplifiers, so that the respective sense amplifier number is equal to the respective bit line number plus the row number.