Abstract: Methods of the present disclosure can include a method for estimating a spatial characteristic of an integrated circuit (IC), the method comprising: calculating a correlation between a dimension of a photoresist layer and exposure to a scanning electron microscope (SEM) for at least one reference IC pattern in the photoresist layer, the correlation providing a relationship between the dimension of the photoresist and the spatial characteristic, wherein the calculating is based on: an SEM image of the at least one reference IC pattern produced from reducing the dimension of the photoresist layer with the SEM from an initial value to a reduced value, the initial value of the dimension, and the reduced value of the dimension; and estimating the spatial characteristic of a target IC based on the correlation.