Abstract: Techniques and structures are disclosed related to coupling to gate-all-around transistors for test and/or debug of an integrated circuit. The gate-all-around transistors, which may also be referred to as 3D stacked transistors or ribbon-FET transistors are contacted directly from the back side or they are contacted using a dedicated probe point on the back side of the gate-all-around transistors. Such contact may be made to probe the devices and/or to provide edit wires to modify the integrated circuit.

Abstract: Enhanced algorithms are provided for finding circuit edit locations which utilize automated conversions from circuit schematic to physical layout design. The enhanced algorithms further include a user interface enabling the user to provide preferences, limitations, and constraints in order to bias the search to be conducted, as well as using the provided design data in order to locate the best positions for particular edit schemes, including net cuts and net joins.

Abstract: A method of planar etching of dissimilar materials with a Focused Ion Beam (FIB) system such as the OptiFIB manufactured by Credence Systems. The method includes adjusting the selectivity between the two materials, which varies when the ratio of the assisting chemistry pressure to the ion dose rate changes. This method can be used in such applications as FIB circuit edit, failure analysis, and cross sectioning.

Abstract: A method and apparatus for optimizing an integrated circuit design for post-fabrication circuit editing and diagnostics. The method and apparatus is specifically directed to adding designed-for-edit modifications and designed-for-diagnostics structures to an integrated circuit design for post-fabrication circuit editing with a charged-particle beam tool. An integrated circuit design may be modified to create efficient and reliable access to specified nodes and structures, such as spare gates, by the charged-particle beam tool during subsequent testing and debugging of the fabricated device. Additionally, structures such as spare gates, spare transistors, spare metal wires, and debug circuitry may be added to an integrated circuit design to provide for easier editing of portions of the design that may fail.

Abstract: Enhanced algorithms are provided for finding circuit edit locations which utilize automated conversions from circuit schematic to physical layout design. The enhanced algorithms further include a user interface enabling the user to provide preferences, limitations, and constraints in order to bias the search to be conducted, as well as using the provided design data in order to locate the best positions for particular edit schemes, including net cuts and net joins.