Abstract: An integrated circuit (IC) device includes a non-volatile memory device with an array of non-volatile memory cells, and an isolation circuit configured to conduct voltage from an internal voltage supply to one of the memory cells during a hidden write operation to the one of the memory cells, and conduct voltage from an external voltage supply to the one of the memory cells during a non-hidden write operation to the one of the memory cells. Current at the external voltage supply can be monitored external to the IC device during the non-hidden write operation, and current of the internal voltage supply is provided by a capacitor that cannot be monitored external to the IC device during the hidden write operation.

Abstract: An integrated circuit (IC) device includes a non-volatile memory device with an array of non-volatile memory cells, and an isolation circuit configured to conduct voltage from an internal voltage supply to one of the memory cells during a hidden write operation to the one of the memory cells, and conduct voltage from an external voltage supply to the one of the memory cells during a non-hidden write operation to the one of the memory cells. Current at the external voltage supply can be monitored external to the IC device during the non-hidden write operation, and current of the internal voltage supply is provided by a capacitor that cannot be monitored external to the IC device during the hidden write operation.

Abstract: The present disclosure provides for semiconductor structures and methods for making semiconductor structures. In one embodiment, isolation regions are formed in a substrate, and wells are formed between the isolation regions. The wells include a first low voltage well and a second low voltage well in a logic region of the substrate, and a memory array well in an NVM region of the substrate. A first layer of oxide is formed over the first low voltage well and the memory array well, and a second layer of oxide is formed over the second low voltage well, the second layer being thinner than the first layer. Gates are formed over the wells, including a first gate over the first low voltage well, a second gate over the second low voltage well, and a memory cell gate over the memory array well. Source/drain extension regions are formed around the gates.

Abstract: The present disclosure provides for semiconductor structures and methods for making semiconductor structures. In one embodiment, isolation regions are formed in a substrate, and wells are formed between the isolation regions. The wells include a first low voltage well and a second low voltage well in a logic region of the substrate, and a memory array well in an NVM region of the substrate. A first layer of oxide is formed over the first low voltage well and the memory array well, and a second layer of oxide is formed over the second low voltage well, the second layer being thinner than the first layer. Gates are formed over the wells, including a first gate over the first low voltage well, a second gate over the second low voltage well, and a memory cell gate over the memory array well. Source/drain extension regions are formed around the gates.

Abstract: A circuit includes a non-volatile memory, a calibration circuit, and a sense amplifier. The sense amplifier senses a state of a memory cell during sensing. The sense amplifier includes a differential circuit having a first input coupled to a reference current source, a second input, and an output coupled to the calibration circuit during a calibration mode. A calibration current source is configured to be coupled to the second input of the differential current sensing circuit during the calibration mode and decoupled from the second input during the sensing mode. A variable current source is coupled to the differential current sensing circuit and the calibration circuit. The calibration circuit tests a plurality of currents of the variable current source during the calibration mode and selects one of the plurality of currents. The sense amplifier senses using the selected one of the plurality of currents.

Abstract: A charge-based voltage multiplier device comprising a charge-pump circuit and a charge-pump controller is provided. The charge-pump circuit is configured to multiply an input voltage signal (Vin) into an output voltage signal (Vout), the charge-pump circuit includes a plurality of charge-pump stages, wherein at least one of the charge-pump stages includes a weighted capacitor array of pump cells. The charge-pump controller is configured to provide a pump cell select to selectively control the weighted capacitor array of pump cells of the at least one of the charge-pump stages of the charge-pump circuit.

Abstract: A reference voltage regulation circuit (143) is provided in which one or more input voltage signals (Vref, Vref?) are selectively coupled to a configurable amplifier (114) which is coupled through a sample and hold circuit (120) to a voltage follower circuit (122) which is coupled in feedback to the configurable amplifier (114) for generating an adjusted output voltage at a circuit output (130), where the voltage follow circuit comprises a resistor divider circuit (126) that is controlled by a calibration signal (Cal<n:0>) generated by a counter circuit (128) selectively coupled to the output of the configurable amplifier when configured as a comparator for generating the calibration signal in response to a clock signal, where the calibration signal represents a voltage error component (Verror, Voffset) that is removed from the circuit output when the calibration signal is applied to the resistor divider circuit during normal operational.

Abstract: A memory including a data line, a sense amplifier, and an array of memory cells. The memory includes a transistor for coupling the data line to memory cells of the array for reading. The transistor is biased at a voltage that is higher than a voltage that the data line is biased during precharging. The transistor is part of a regulation circuit. The regulation circuit includes transistors with a higher dielectric breakdown voltage than transistors of the sense amplifier.

Abstract: A memory including a data line, a sense amplifier, and an array of memory cells. The memory includes a transistor for coupling the data line to memory cells of the array for reading. The transistor is biased at a voltage that is higher than a voltage that the data line is biased during precharging. The transistor is part of a regulation circuit. The regulation circuit includes transistors with a higher dielectric breakdown voltage than transistors of the sense amplifier.

Abstract: A reference voltage regulation circuit (143) is provided in which one or more input voltage signals (Vref, Vref?) are selectively coupled to a configurable amplifier (114) which is coupled through a sample and hold circuit (120) to a voltage follower circuit (122) which is coupled in feedback to the configurable amplifier (114) for generating an adjusted output voltage at a circuit output (130), where the voltage follow circuit comprises a resistor divider circuit (126) that is controlled by a calibration signal (Cal<n:0>) generated by a counter circuit (128) selectively coupled to the output of the configurable amplifier when configured as a comparator for generating the calibration signal in response to a clock signal, where the calibration signal represents a voltage error component (Verror, Voffset) that is removed from the circuit output when the calibration signal is applied to the resistor divider circuit during normal operational.

Abstract: A level converter comprises first and second latches, and first through fourth transistors. The first latch has first and second power supply terminals, and first and second nodes. The second latch has third and fourth power supply terminals, and third and fourth nodes. The first transistor has a first current electrode coupled to the first node, a control electrode coupled to receive a first bias voltage, and a second current electrode. The second transistor has a first current electrode coupled to the second current electrode of the first transistor, a second current electrode coupled to the third node, and a control electrode coupled to receive a second bias voltage. The third transistor has a first current electrode coupled to the second node, a control electrode coupled to receive the first bias voltage, and a second current electrode.

Abstract: A charge-based voltage multiplier device comprising a charge-pump circuit and a charge-pump controller is provided. The charge-pump circuit is configured to multiply an input voltage signal (Vin) into an output voltage signal (Vout), the charge-pump circuit includes a plurality of charge-pump stages, wherein at least one of the charge-pump stages includes a weighted capacitor array of pump cells. The charge-pump controller is configured to provide a pump cell select to selectively control the weighted capacitor array of pump cells of the at least one of the charge-pump stages of the charge-pump circuit.

Abstract: A level converter comprises first and second latches, and first through fourth transistors. The first latch has first and second power supply terminals, and first and second nodes. The second latch has third and fourth power supply terminals, and third and fourth nodes. The first transistor has a first current electrode coupled to the first node, a control electrode coupled to receive a first bias voltage, and a second current electrode. The second transistor has a first current electrode coupled to the second current electrode of the first transistor, a second current electrode coupled to the third node, and a control electrode coupled to receive a second bias voltage. The third transistor has a first current electrode coupled to the second node, a control electrode coupled to receive the first bias voltage, and a second current electrode.

Abstract: A memory includes a plurality of memory cells, a sense amplifier coupled to at least one of the plurality of memory cells, a temperature dependent current generator comprising a plurality of selectable temperature dependent current sources for generating a temperature dependent current, a temperature independent current generator comprising a plurality of selectable temperature independent current sources for generating a temperature independent current, and a summer coupled to the temperature dependent current generator and the temperature independent current generator for combining the temperature dependent current and the temperature independent current to generate a reference current for use by the sense amplifier. A temperature coefficient of the reference current is approximately a same as a temperature coefficient of a memory cell current of at least one of the plurality of memory cells.

Abstract: A charge pump system including a clock circuit and a charge pump circuit is provided. The clock circuit provides a first clock with a frequency based on a memory block select signal indicative of load capacitance of a charge node. The charge pump circuit receives the first clock and charges the charge node at a rate based on the frequency of the first clock and the load capacitance of the charge node. The memory block select signal indicates which of the memory blocks are coupled to the charge node and thus indicates the load capacitance of the charge node. The frequency of the first clock is adjusted based on the load capacitance of the selected block so that the slew rate of the charge node is about the same. Thus, the slew rate of the voltage ramp on the charge node is about the same regardless of the load capacitance.

Abstract: A memory includes a plurality of memory cells, a sense amplifier coupled to at least one of the plurality of memory cells, a temperature dependent current generator comprising a plurality of selectable temperature dependent current sources for generating a temperature dependent current, a temperature independent current generator comprising a plurality of selectable temperature independent current sources for generating a temperature independent current, and a summer coupled to the temperature dependent current generator and the temperature independent current generator for combining the temperature dependent current and the temperature independent current to generate a reference current for use by the sense amplifier. A temperature coefficient of the reference current is approximately a same as a temperature coefficient of a memory cell current of at least one of the plurality of memory cells.

Abstract: A charge pump system including a clock circuit and a charge pump circuit is provided. The clock circuit provides a first clock with a frequency based on a memory block select signal indicative of load capacitance of a charge node. The charge pump circuit receives the first clock and charges the charge node at a rate based on the frequency of the first clock and the load capacitance of the charge node. The memory block select signal indicates which of the memory blocks are coupled to the charge node and thus indicates the load capacitance of the charge node. The frequency of the first clock is adjusted based on the load capacitance of the selected block so that the slew rate of the charge node is about the same. Thus, the slew rate of the voltage ramp on the charge node is about the same regardless of the load capacitance.

Abstract: An integrated circuit includes a memory (10). The memory (10) includes an array (12) of non-volatile memory cells. Each memory cell (14) of the array (12) includes a plurality of terminals comprising: a control gate, a charge storage region, a source, a drain, a well terminal, and a deep well terminal. Following an erase operation of the array (12), the erase voltages are discharged from each of the memory cells. A discharge rate control circuit (11) controls the discharging of terminals of the memory cell. The discharge rate control circuit (11) includes a reference current generator (34) for providing a reference current. A first current mirror (46) is coupled to the reference current generator (34) and provides a first predetermined discharge current for discharging the control gate, drain, and source. A second current mirror (36) is coupled to the reference current generator (34) and provides a second predetermined discharge current for discharging the well terminals after the erase operation.

Abstract: An integrated circuit includes a memory (10). The memory (10) includes an array (12) of non-volatile memory cells. Each memory cell (14) of the array (12) includes a plurality of terminals comprising: a control gate, a charge storage region, a source, a drain, a well terminal, and a deep well terminal. Following an erase operation of the array (12), the erase voltages are discharged from each of the memory cells. A discharge rate control circuit (11) controls the discharging of terminals of the memory cell. The discharge rate control circuit (11) includes a reference current generator (34) for providing a reference current. A first current mirror (46) is coupled to the reference current generator (34) and provides a first predetermined discharge current for discharging the control gate, drain, and source. A second current mirror (36) is coupled to the reference current generator (34) and provides a second predetermined discharge current for discharging the well terminals after the erase operation.