Patents by Inventor Ta-Hui Wang
Ta-Hui Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7916551Abstract: A method of programming a first cell in a memory, wherein the first cell has a first S/D region and shares a second S/D region with a second cell that has a third S/D region opposite to the second S/D region. The channels of the first and the second cells are turned on, a first voltage is applied to the first S/D region, a second voltage is applied to the second S/D region and a third voltage is applied to the third S/D region. The second voltage is between the first voltage and the third voltage, and the first to third voltages make carriers flow from the third S/D region to the first S/D region and cause hot carriers in the channel of the first cell to be injected into the charge storage layer of the first cell.Type: GrantFiled: June 13, 2008Date of Patent: March 29, 2011Assignee: MACRONIX International Co., Ltd.Inventors: Wen-Jer Tsai, Ta-Hui Wang, Chih-Wei Lee
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Publication number: 20090116294Abstract: A method of programming a first cell in a memory, wherein the first cell has a first S/D region and shares a second S/D region with a second cell that has a third S/D region opposite to the second S/D region. The channels of the first and the second cells are turned on, a first voltage is applied to the first S/D region, a second voltage is applied to the second S/D region and a third voltage is applied to the third S/D region. The second voltage is between the first voltage and the third voltage, and the first to third voltages make carriers flow from the third S/D region to the first S/ID region and cause hot carriers in the channel of the first cell to be injected into the charge storage layer of the first cell.Type: ApplicationFiled: June 13, 2008Publication date: May 7, 2009Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Wen-Jer Tsai, Ta-Hui Wang, Chih-Wei Lee
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Patent number: 7243277Abstract: A memory combines plural memory cells for storing data wherein the differential stages voltage levels of memory cells are not limited in square value of 2 and can be improved linearly. The feature of the present invention can also increase memory capacity without increasing memory area. Furthermore it can remain voltage levels which cannot express 0 and 1 combination for error erasure messages when data is read. For efficient usage of memory, the increased memory capacity is not only for storing data but also for storing error correction scheme to assure the veracity of the storing data and improve producing yield and reliability for multilevel memory systems.Type: GrantFiled: July 18, 2005Date of Patent: July 10, 2007Assignee: National Chiao Tung UIniversityInventors: Jieh-Tsorng Wu, Ta-Hui Wang, Hsie-Chia Chang
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Publication number: 20060015793Abstract: A memory combines plural memory cells for storing data wherein the differential stages voltage levels of memory cells are not limited in square value of 2 and can be improved linearly. The feature of the present invention can also increase memory capacity without increasing memory area. Furthermore it can remain voltage levels which cannot express 0 and 1 combination for error erasure messages when data is read. For efficient usage of memory, the increased memory capacity is not only for storing data but also for storing error correction scheme to assure the veracity of the storing data and improve producing yield and reliability for multilevel memory systems.Type: ApplicationFiled: July 18, 2005Publication date: January 19, 2006Inventors: Jieh-Tsorng Wu, Ta-Hui Wang, Hsie-Chia Chang
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Publication number: 20030089935Abstract: A non-volatile semiconductor memory device with a multi-layer gate insulating structure is provided. The non-volatile semiconductor memory device comprises a gate insulating structure formed between a gate and a channel region, which includes a top silicon nitride layer, an intermediate silicon nitride layer and a bottom silicon nitride layer. When an electric field is applied between the gate and a drain region beside the channel region, hot carriers exhibit a direct tunneling across the bottom silicon nitride layer from the drain region for a write-erase operation. The hot carriers having exhibited the direct tunneling from the drain region are trapped into the intermediate silicon nitride layer.Type: ApplicationFiled: November 13, 2001Publication date: May 15, 2003Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Tso-Hung Fan, Tao-Cheng Lu, Samuel Pan, Ta-Hui Wang
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Patent number: 6563752Abstract: A qualification test method for a non-volatile memory includes determining a relation curve between the programming voltage and the lifetime of the memory cell. A programming voltage with respect to the memory array within the expected lifetime is estimated. According to the relation curve, the accelerating test voltage and the test time period corresponding to the programming voltage operated in the expected lifetime are computed out. The test is performed for the test time period under the accelerating test voltage. All the memory cells at the programmed state are tested to see if the original programmed state still remains. If the programmed state remains, the memory array is judged to have the life period. If the programmed state does not remain, the memory array is judged to have no the life period.Type: GrantFiled: August 30, 2001Date of Patent: May 13, 2003Assignee: Macronix International Co., Ltd.Inventors: Wen-Jer Tsai, Nian-Kai Zous, Ta-Hui Wang
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Patent number: 6552921Abstract: A circuit to simulate the polarization relaxation phenomenon of the ferroelectric memory. The circuit has a MOS transistor, a ferroelectric capacitor, a capacitor, and a relaxation voltage source. The gate of the MOS transistor is coupled to a word line and the source of the MOS transistor is coupled to a bit line. A first electrode of the ferroelectric capacitor is coupled to the drain of the MOS transistor and the second electrode of the ferroelectric capacitor is coupled to a plate line. A first electrode of the capacitor is coupled to the drain of the MOS transistor. A first electrode of the relaxation voltage source is coupled to the second electrode of the capacitor, and the second electrode of the relaxation voltage source is coupled to a ground. The capacitance of the capacitor mentioned above is selectively far smaller than the capacitance of the bit line.Type: GrantFiled: January 15, 2002Date of Patent: April 22, 2003Assignee: Macronix International Co., Ltd.Inventors: Ching-Wei Tsai, Shyue-Yi Lee, Ta-Hui Wang
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Publication number: 20030058682Abstract: A circuit to simulate the polarization relaxation phenomenon of the ferroelectric memory The circuit has a MOS transistor, a ferroelectric capacitor, a capacitor, and a relaxation voltage source. The gate of the MOS transistor is coupled to a word line and the source of the MOS transistor is coupled to a bit line A first electrode of the ferroelectric capacitor is coupled to the drain of the MOS transistor and the second electrode of the ferroelectric capacitor is coupled to a plate line. A first electrode of the capacitor is coupled to the drain of the MOS transistor. A first electrode of the relaxation voltage source is coupled to the second electrode of the capacitor, and the second electrode of the relaxation voltage source is coupled to a ground. The capacitance of the capacitor mentioned above is selectively far smaller than the capacitance of the bit line. The output voltage of the relaxation voltage source is a logarithmic time dependence.Type: ApplicationFiled: January 15, 2002Publication date: March 27, 2003Inventors: Ching-Wei Tsai, Shyue-Yi Lee, Ta-Hui Wang
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Patent number: 6512696Abstract: A method of programming and erasing a SNNNS type non-volatile memory cell is provided. The programming operation is performed by channel hot electron injection from a drain side to an intermediate silicon nitride layer. The erasing operation is performed by channel hot hole injection from a drain side to an intermediate silicon nitride layer. The SNNNS type non-volatile memory cell provides highly efficient hot carrier injection under low applied voltages, both for programming and erasing operations. Thus, the present method provides improved performance characteristics such as shorter programming/erasing times and lower applied voltages.Type: GrantFiled: November 13, 2001Date of Patent: January 28, 2003Assignee: Macronix International Co., Ltd.Inventors: Tso-Hung Fan, Tao-Cheng Lu, Samuel Pan, Ta-Hui Wang
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Patent number: 6512710Abstract: A reliability test method for a non-volatile memory. A relation curve of gate voltage versus read current degradation rate is obtained. The read current degradation rate of an actual gate voltage is estimated. From the relation curve, an accelerated test gate voltage and a test time corresponding to the actual gate voltage are obtained. With the accelerated test gate voltage, the test is continuously performed within the test time. Afterward, a test result of the memory is then obtained and, by the result, it is judged whether the data is valid or not. If the data is right (retained), the memory can be guarantied to have an expected lifetime; if the data is wrong (lost), the memory is judged as fails to pass the lifetime test.Type: GrantFiled: December 4, 2001Date of Patent: January 28, 2003Assignee: Macronix International Co., Ltd.Inventors: Wen-Jer Tsai, Lan Ting Huang, Nian-Kai Zous, Ta-Hui Wang
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Patent number: 6445614Abstract: An accelerated test for a non-volatile memory. A threshold voltage variation standard for assessment is selected. A set of negative gate bias voltages is applied to the gate terminals of the non-volatile memory to conduct the accelerated testing and obtain a test result. A curve relating lifetime and negative gate bias voltage is derived from the test result. According to the threshold voltage variation standard, the lifetime of the non-volatile memory is found. A word line negative gate bias voltage generator is coupled to a word line driver to apply a set of negative gate bias voltages to the gate terminals of programmed memory cells and conduct an accelerated testing.Type: GrantFiled: August 14, 2001Date of Patent: September 3, 2002Assignee: Macronix International Co., Ltd.Inventors: Wen-Jer Tsai, Nian-Kai Zous, Ta-Hui Wang
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Publication number: 20020036939Abstract: A qualification test method for a non-volatile memory includes determining a relation curve between the programming voltage and the lifetime of the memory cell. A programming voltage with respect to the memory array within the expected lifetime is estimated. According to the relation curve, the accelerating test voltage and the test time period corresponding to the programming voltage operated in the expected lifetime are computed out. The test is performed for the test time period under the accelerating test voltage. All the memory cells at the programmed state are tested to see if the original programmed state still remains. If the programmed state remains, the memory array is judged to have the life period. If the programmed state does not remain, the memory array is judged to have no the life period.Type: ApplicationFiled: August 30, 2001Publication date: March 28, 2002Inventors: Wen-Jer Tsai, Nian-Kai Zous, Ta-Hui Wang