Abstract: A field wheat stem tillering number extraction method, including: acquiring field wheat point clouds by means of a LiDAR, and extracting any row of wheat point clouds in a research area; projecting a Y axis to a plane, and retaining an X and Z axis; applying adaptive layering to obtain number of clusters of the wheat row; applying hierarchical clustering analysis to obtain tillering number of each wheat cluster; and further obtaining stem tillering number of the whole wheat row, so as to extract a field wheat stem tillering number. The feasibility of an algorithm is verified by comparing the wheat stem tillering number extracted by means of the method with an actually measured field stem tillering number, and the method realizes rapid, accurate and nondestructive extraction of a large-field crop stem tillering number and provides theoretical basis and technical support for extraction of the field wheat stem tillering number.

Abstract: Method and apparatus for visualization of a touch panel to object distance (TOD) in X-ray imaging. The method includes: obtaining a three-dimensional image of a to-be-detected subject that includes an object; determining a TOD; generating a first identifier at a position of a touch panel in the three-dimensional image; and generating a second identifier in the three-dimensional image, where a distance between the first identifier and the second identifier corresponds to the TOD.

Abstract: A path delay prediction method for an integrated circuit based on feature selection and deep learning. First, an integrated feature selection method based on filter methods and wrapper methods is established to determine an optimal feature subset. Timing information and physical topological information of a circuit are then extracted to be used as input features of a model, and local physical and timing expressions of cells in circuit paths are captured by means of the convolution calculation mechanism of a convolutional neural network. In addition, a residual network is used to calibrate a path delay. Compared with traditional back-end design processes, the path delay prediction method provided by the invention has remarkable advantages in prediction accuracy and efficiency and has great significance in accelerating the integrated circuit design process.

Abstract: A post-routing path delay prediction method for a digital integrated circuit is provided. First, physical design and static timing analysis are performed on a circuit by a commercial physical design tool and a static timing analysis tool, timing and physical information of a path is extracted before routing of the circuit to be used as input features of a prediction model, then the timing and physical correlation of all stages of cells in the path is captured by a transformer network, a predicted post-routing path delay is calibrated by a residual prediction structure, and finally, a final predicted post-routing path delay is output.

Abstract: A path delay prediction method for an integrated circuit based on feature selection and deep learning. First, an integrated feature selection method based on filter methods and wrapper methods is established to determine an optimal feature subset. Timing information and physical topological information of a circuit are then extracted to be used as input features of a model, and local physical and timing expressions of cells in circuit paths are captured by means of the convolution calculation mechanism of a convolutional neural network. In addition, a residual network is used to calibrate a path delay. Compared with traditional back-end design processes, the path delay prediction method provided by the invention has remarkable advantages in prediction accuracy and efficiency and has great significance in accelerating the integrated circuit design process.

Abstract: A post-routing path delay prediction method for a digital integrated circuit is provided. First, physical design and static timing analysis are performed on a circuit by a commercial physical design tool and a static timing analysis tool, timing and physical information of a path is extracted before routing of the circuit to be used as input features of a prediction model, then the timing and physical correlation of all stages of cells in the path is captured by a transformer network, a predicted post-routing path delay is calibrated by a residual prediction structure, and finally, a final predicted post-routing path delay is output.

Abstract: One or more example embodiments relates to a computer-implemented a method for providing a label of a body part on an X-ray image, comprising receiving input data, wherein the input data is based on a red, green and blue (RGB) image of the body part, a depth image of the body part and an X-ray image of the body part; applying at least one trained function to the input data to generate output data, wherein the output data is the label of the body part, the label indicating a right body part or a left body part; and providing the output data.

Abstract: For testing a device under test (“DUT”) a test specification is converted in a computer system by a pin vector generator process, which includes generating test vectors. The DUT has numerous input pins and such a pin vector is for a signal to drive one such pin. The pin vectors are compressed and saved. Ones of the pin vectors are loaded, upon initialization of a test, into a pipeline having a series of memory stages and extending from the computer system to channel cards in a test head. The pipeline is operated in data transfer cycles, delivering W bits per cycle. The pin vectors are decompressed at the respective channel cards in decompressor read cycles. X bits are read per decompressor cycle, W being greater than X, so that the pipeline may perform its data transfer cycles less frequently than the decompressor performs its read cycles.

Abstract: A mechanism is provided for highlighting items of interest in a set of web pages. The link highlighting mechanism may retrieve and examine web pages referenced by the instant web page. In this manner, the link highlighting mechanism may crawl through a set of web pages and highlight links that direct the user to the item of interest. The link highlighting mechanism may also record a user's click sequence to determine the most recently or most frequently visited links. The mechanism may then highlight the most recently or most frequently visited links to allow easy and quick navigation to items that are of particular interest to the user. The user may also enter properties of an item of interest, such as a file type or link type. The link highlighting mechanism examines a web page for items and links that match the property. If the user is using a mobile computing device or is otherwise operating with limited bandwidth, the highlighting mechanism may reside on a server.

Abstract: A memory array includes a storage unit with a number of sections and decoders coupled to respective ones of the sections for decoding an N-bit address signal and responsively asserting a signal on one of the word lines selected by the address signal. Local clock buffers are coupled to respective ones of the decoders for receiving a clock signal and an address signal including M most-significant bits of the N-bit address signal and generating respective timing signals. The decoders receive the timing signal from their respective local clock buffers. Each decoder is operable to alternately precharge and evaluate the N-bit address signal responsive to phases of the timing signal. Each local clock buffer is operable, responsive to a state of the M bits of the address signal, for selecting between holding its timing signal in a deasserted state and enabling its timing signal to follow the clock signal.

Abstract: The present invention allows for the simultaneous transmission of two digital signals from one integrated circuit to another. The two digital signals are encoded utilizing a voltage divider circuit and are then transmitted by one transmission line to the second integrated circuit chip. The second integrated circuit chip decodes the first digital signal and then utilizes this decoded digital signal to further decode the second digital signal.

Abstract: An exclusive OR circuit (10) includes an input stage (11) and a control arrangement (12,13) for controlling an exclusive OR logical evaluation. The control arrangement includes a pre-charge stage (12) which responds to a first level clock signal to enable the desired exclusive OR logical evaluation. The input stage (11) is connected to receive a first input signal and a second input signal and is also connected to an evaluation node (23). When the logic state of one input signal is unequal to the logic state of the other input signal, the input stage (11) couples the evaluation node (23) to ground. An output stage (13) of the control arrangement inverts the signal at an internal node (24) to produce the output from the exclusive OR circuit. A pre-charge stage (12) couples the internal node (24) to the evaluation node (23) only in response to a "high" clock signal.

Abstract: The present invention allows for the simultaneous transmission of two digital signals from one integrated circuit to another. The two digital signals are encoded utilizing a voltage divider circuit and are then transmitted by one transmission line to the second integrated circuit chip. The second integrated circuit chip decodes the first digital signal and then utilizes this decoded digital signal to further decode the second digital signal.

Abstract: The present invention facilitates communication of signals from circuitry implemented with a first CMOS technology requiring a first voltage level supply for operation to circuitry implemented with a second CMOS technology requiring a second voltage level supply for operation, wherein the first and second voltage level supplies are not equal. The present invention receives from the circuitry implemented with a first CMOS technology a signal which has a first voltage level that is not acceptable for input into the circuitry implemented with a second CMOS technology. This signal is converted to a second voltage level that is acceptable for input into the circuitry implemented with a second CMOS technology, and then transmitted to the circuitry implemented with a second CMOS technology requiring a second voltage level supply for operation.

Abstract: Thin-film conductor technology is utilized to form resistors of precisely controlled value within the interior of multi-chip modules to properly terminate network circuits which interconnect one or more chips with either output pin connections or other chips on the multi-chip module. By forming and disposing the resistors within the interior of the multi-chip module, the terminating resistors may be manufactured during the multi-chip module manufacturing process. This approach preserves valuable surface area available for interconnecting the computer chips to the multi-chip module rather than consuming scarce surface area with termination resistors and other circuit elements necessary to adapt the multi-chip module and the other computer chips to each other.

Abstract: The present invention facilitates communication of signals from circuitry implemented with a first CMOS technology requiring a first voltage level supply for operation to circuitry implemented with a second CMOS technology requiring a second voltage level supply for operation, wherein the first and second voltage level supplies are not equal. The present invention receives from the circuitry implemented with a first CMOS technology a signal which has a first voltage level that is not acceptable for input into the circuitry implemented with a second CMOS technology. This signal is converted to a second voltage level that is acceptable for input into the circuitry implemented with a second CMOS technology, and then transmitted to the circuitry implemented with a second CMOS technology requiring a second voltage level supply for operation.

Abstract: A CMOS driver/receiver pair is provided which includes a non-inverting buffer in the input path to a differential receiver circuit. The non-inverting buffer allows a plurality of different voltages, and corresponding voltage swings, to be possible. This allows the differential receiver to compare the input voltage received from the transmission line with the output from its associated driver. Therefore, the receiver is capable of determining the voltage level (and the corresponding logic level) input from the transmission at the same time its associated driver is outputting a logic signal to another driver/receiver pair, via the transmission line. A single voltage source is utilized to provide multiple positive voltages to the differential receivers, such that differences in voltage levels which correspond to different logical combinations of "1" and "0" can be determined by the receiver.

Abstract: A clock distribution system for a data processing system is implemented in CMOS technology wherein a full-swing differential clock signal is converted to a low-voltage swing differential clock signal by a driver's circuit and then returned to a full-swing differential clock signal at each receiver circuit.

Abstract: The present invention includes an output circuit for a driver on a first chip that will cause an unterminated transmission line to create a predetermined voltage reflection. This reflection will then be added to the output of the driver circuit to obtain a voltage level capable of switching the receiver circuit, located on a second chip. Further, the impedance of the driver can be varied to adjust the voltage level of the signal being transmitted to the receiver, in order to reduce noise margins and cause the receiver to switch more quickly. Additionally, the transmission line impedance can also be modified to create overshoot, thereby allowing chips with dissimilar voltage levels to communicate with one another.

Abstract: A circuit for supplying a reference voltage from a single data input voltage source is provided which utilizes a delay circuit in conjunction with a source follower circuit to provide a separate reference voltage to a differential circuit. The data input signal is provided concurrently to the source follower circuit and the delay. The source follower circuit includes an "N" type transistor which has its source connected to the source of a "P" type transistor. The delay circuit is provided to delay, or "hold off" the data input signal until the signal is through the source follower and ready for input to the differential circuit. By using the delay, the data input signal and the reference signal (output from the source follower) are input to the differential circuit simultaneously. The threshold voltage drop across the gate and source of the transistors in the source follower circuit provide the reference voltage, which follows the data input voltage.