Abstract: An analysis method and an electronic apparatus for breast image are provided. The method includes the following steps. One or more breast ultrasound images are obtained. The breast ultrasound images are used for forming a three-dimensional (3D) breast model. A volume of interest (VOI) in the breast ultrasound image is obtained by applying a detection model on the 3D breast model. The VOI is compared with a tissue segmentation result. The VOI is determined as a false positive according to a compared result between the VOI and the tissue segmentation result. The compared result includes that the VOI is located at a glandular tissue based on the tissue segmentation result. In response to the VOI being located in the glandular tissue of the tissue segmentation result, the VOI is compared with the lactiferous duct in the 3D breast model.

Abstract: A first group of semiconductor fins are over a first region of a substrate, the substrate includes a first stepped profile between two of the first group of semiconductor fins, and the first stepped profile comprises a first lower step, two first upper steps, and two first step rises extending from opposite sides of the first lower step to the first upper steps. A second group of semiconductor fins are over a second region of the substrate, the substrate includes a second stepped profile between two of the second group of semiconductor fins, and the second stepped profile comprises a second lower step, two second upper steps, and two second step rises extending from opposite sides of the second lower step to the second upper steps, in which the second upper steps are wider than the first upper steps in the cross-sectional view.

Abstract: Example methods are provided to improve placement of an adaptor (210,220) to a mobile computing device (100) to measure a test strip (221) coupled to the adaptor (220) with a camera (104) and a screen (108) on a face of the mobile computing device (100). The method may include displaying a light area on a first portion of the screen (108). The first portion may be adjacent to the camera (104). The light area and the camera (104) may be aligned with a key area of the test strip (221) so that the camera (104) is configured to capture an image of the key area. The method may further include providing first guiding information for a user to place the adaptor (210,220) to the mobile computing device (100) according to a position of the light area on the screen (108).

Abstract: A memory device includes a memory bank with a memory cell connected to a local bit line and a word line. A first local data latch is connected to the local bit line and has an enable terminal configured to receive a first local clock signal. A word line latch is configured to latch a word line select signal, and has an enable terminal configured to receive a second local clock signal. A first global data latch is connected to the first local data latch by a global bit line, and the first global data latch has an enable terminal configured to receive a global clock signal. A global address latch is connected to the word line latch and has an enable terminal configured to receive the global clock signal. A bank select latch is configured to latch a bank select signal, and has an enable terminal configured to receive the second local clock signal.

Abstract: A circuit test structure includes a chip including a conductive line which traces a perimeter of the chip. The circuit test structure further includes an interposer electrically connected to the chip, wherein the conductive line is over both the chip and the interposer. The circuit test structure further includes a test structure connected to the conductive line. The circuit test structure further includes a testing site, wherein the test structure is configured to electrically connect the testing site to the conductive line.

Abstract: A semiconductor device structure includes a fin structure formed over a substrate. The structure also includes nanostructures formed over the fin structure. The structure also includes a gate structure wrapped around the nanostructures. The structure also includes a first inner spacer formed beside the gate structure. The structure also includes a second inner spacer formed beside the first inner spacer. The structure also includes spacer layers formed over opposite sides of the gate structure above the nanostructures. The structure also includes source/drain epitaxial structures formed over opposite sides of the fin structure. The second inner spacer is partially embedded in the source/drain epitaxial structures.

Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.

Abstract: A semiconductor structure, comprising a redistribution layer (RDL) including a dielectric layer and a conductive trace within the dielectric layer; a first conductive member disposed over the RDL and electrically connected with the conductive trace; a second conductive member disposed over the RDL and electrically connected with the conductive trace; a first die disposed over the RDL; a second die disposed over the first die, the first conductive member and the second conductive member; and a connector disposed between the second die and the second conductive member to electrically connect the second die with the conductive trace, wherein the first conductive member is electrically isolated from the second die.

Abstract: The disclosure provides an electronic device, including a circuit board, multiple semiconductor components, a first light reflecting structure, and a second light reflecting structure. The circuit board includes a substrate, and the substrate may have a first surface and at least one side surface. The multiple semiconductor components are disposed on the first surface. The first light reflecting structure is disposed on the first surface. The second light reflecting structure is disposed on the first surface and the at least one side surface.

Abstract: Disclosed herein are related to a memory system including unit storage circuits. In one aspect, each of the unit storage circuits abuts an adjacent one of the unit storage circuits. In one aspect, each of the unit storage circuits includes a first group of memory cells, a second group of memory cells, a first sub-word line driver to apply a first control signal to the first group of memory cells through a first sub-word line extending along a direction, and a second sub-word line driver to apply a second control signal to the second group of memory cells through a second sub-word line extending along the direction. In one aspect, the memory system includes a common word line driver abutting one of the unit storage circuits and configured to apply a common control signal to the unit storage circuits through a word line extending along the direction.

Abstract: In an embodiment, a chemical mechanical planarization (CMP) system includes: a monolithic platen within a platen housing, wherein the monolithic platen is formed of a single piece of material, wherein the monolithic platen includes: a first portion within a first opening, and a second portion within a second opening, wherein the first portion has a different diameter than the second portion; and a polishing fluid delivery module above the monolithic platen, wherein the polishing fluid delivery module is configured to deliver slurry to the monolithic platen during performance of CMP.

Abstract: A touch function setting method is provided. The method comprising: receiving a sequence parameter which includes multiple clicks, each of the clicks is corresponding to one of areas of a touch panel or screen; receiving a function parameter corresponding to the sequence parameter, the function parameter is corresponding to activate a function; and storing a group of touch function parameters, which includes the sequence parameter and the function parameter.

Abstract: A cell culture device includes a culture unit, a gas supply unit, a first pressure unit, at least one inspecting unit and a control unit. The culture unit contains a cell culture liquid. The gas supply unit, connected with the culture unit, is used for transmitting a culture gas into the culture unit. The first pressure unit, connected with the culture unit, is used for applying a pressure to the cell culture liquid in the culture unit. The at least one inspecting unit, connected with the culture unit, is used for receiving the cell culture liquid for inspection. The control unit, electrically coupled with the culture unit, the first pressure unit, the gas supply unit and the at least one inspecting unit, is used for monitoring corresponding condition parameters to determine respective operations. In addition, a cell culture method for the cell culture device is also provided.

Abstract: A display device is provided. The display device includes a device housing, a knob, a restriction unit and a screen panel. The knob is rotatably connected to the device housing, wherein the knob comprises a latch and a plurality of teeth, the knob is adapted to be rotated between a first knob location and a second knob location, and when the knob is in the first knob location, the latch protrudes from the device housing, and when the knob is in the second knob location, the latch is received in the device housing. The restriction unit is disposed in the device housing, wherein the restriction unit is adapted to be connected to one of the teeth to restrict the knob. The screen panel is detachably connected to the device housing. The display device can be easily detached from a display system.

Abstract: An illumination system, configured to provide an illumination beam, is provided. The illumination system includes a first excitation light source, a wavelength conversion element, and a controller. The first excitation light source is configured to provide a first excitation beam. The wavelength conversion element is located on a transmission path of the first excitation beam. The wavelength conversion element includes multiple wavelength conversion regions and multiple non-wavelength conversion regions. The controller controls whether the first excitation light source emits light. During a first time interval, the controller turns off the first excitation light source. During a second time interval, the controller controls the first excitation light source to emit light. The first excitation beam is transmitted to one of the wavelength conversion regions to form a converted beam. The illumination beam includes the converted beam. Another illumination system and multiple projection devices are also provided.

Abstract: A method for in vitro activation and/or expansion of immune cells is provided, including the steps of: a) providing magnetic particles having multi-protrusive surface modified with at least one type of immuno-inducing substance, in which each magnetic particle includes a copolymer core, a polymer layer, a magnetic substance layer, and a silicon-based layer from the inside to the outside; b) providing a cell solution including at least one type of immune cell in the cell solution; and c) bringing the magnetic particles in contact with the cell solution, in which the at least one type of immuno-inducing substance on the surface of the magnetic particle activates and/or expands the at least one type of immune cell in the cell solution.

Abstract: A protection circuit including an auxiliary winding, a rectifier unit, the filter unit, a voltage divider unit and a controller is provided. The auxiliary winding is configured to induce an AC voltage. The rectifier unit is coupled to the auxiliary winding and configured to rectify the AC voltage into a DC voltage. The filter unit is coupled to the rectifier unit and configured to filter the DC voltage into a DC filter voltage. The voltage divider unit is coupled to the rectifier unit and the filter unit to transmit the DC filter voltage. The controller is coupled to the voltage divider unit and configured to detect a partial voltage of the DC filter voltage and detect whether to activate a protection mechanism according to the partial voltage.

Abstract: A display panel includes a substrate, a first isolation structure, a second isolation structure and a plurality of light emitting structures. The first isolation structure is disposed on the substrate and includes a plurality of through holes. The second isolation substrate is laminated on the first isolation substrate and fills up the plurality of through holes of the first isolation substrate. The plurality of light emitting structures are disposed on the substrate and are isolated from each other via the second isolation structure.

Abstract: An information capturing device includes a positioning unit, an audiovisual recording unit and a control unit. The positioning unit tracks and acquires multiple satellite signals and calculates positioning data and a moving speed according to the satellite signals. The control unit is activated the audiovisual recording to perform audiovisual recording and controls the positioning unit to enter a first operation mode. In the first operation mode, the positioning unit updates positioning data according to a first cycle. While the audiovisual recording is performed, the control unit reads the moving speed from the positioning unit, and the control unit controls the positioning unit to switch to a second operation mode when the moving speed is less than or equal to a first threshold. In the second operation mode, the positioning unit updates the positioning data according to a second cycle longer than the first cycle.

Abstract: A transmitter circuit is provided. The transmitter circuit has a first transmission node and a second transmission node and includes a first resistor, a second resistor, a third resistor, a fourth resistor, and a driving circuit. The driving circuit includes a first transistor group, a second transistor group, a third transistor group, and a fourth transistor group. The first resistor is coupled between a first output terminal and the first transmission node. The second resistor is coupled between a second output terminal and the second transmission node. The third resistor is coupled between a third output terminal and the first transmission node. The fourth resistor is coupled between a fourth output terminal and the second transmission node. The first, second, third, and fourth transistor groups are coupled to a first and a second reference voltages and electrically connected to the first, second, third, and fourth output terminals, respectively.