Patents by Inventor Tai-An Lu
Tai-An Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240162833Abstract: A power supply unit supplies power to a load, and the power supply unit includes a power factor corrector, a DC conversion module, and an isolated conversion module. The power factor corrector is plugged into a first main circuit board and converts an AC power into a DC power. The DC conversion module is plugged into the first main circuit board and converts the DC power into a main power. The isolated conversion module includes a bus capacitor, the bus capacitor is coupled to the DC conversion module through a first power copper bar, and coupled to the power factor corrector through a second power copper bar. The first power copper bar and the second power copper bar are arranged on a side opposite to the first main circuit board, and are arranged in parallel with the first main circuit board.Type: ApplicationFiled: November 13, 2023Publication date: May 16, 2024Inventors: Yi-Sheng CHANG, Cheng-Chan HSU, Chia-Wei CHU, Chun-Yu YANG, Deng-Cyun HUANG, Yi-Hsun CHIU, Chien-An LAI, Yu-Tai WANG, Chi-Shou HO, Zhi-Yuan WU, Ko-Wen LU
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Patent number: 11959101Abstract: A cell activation reactor and a cell activation method are provided. The cell activation reactor includes a body, a rotating part, an upper cover, a microporous film, and multiple baffles. The body has an accommodating space, which is suitable for accommodating multiple cells and multiple magnetic beads. The rotating part is disposed in the accommodating space and includes multiple impellers. The microporous film is disposed in the accommodating space and covers multiple holes of the accommodating space. The baffles are disposed in the body. When the rotating part is driven to rotate, the interaction between the baffles and the impellers separates the cells and the magnetic beads.Type: GrantFiled: November 26, 2021Date of Patent: April 16, 2024Assignee: Industrial Technology Research InstituteInventors: Ting-Hsuan Chen, Kuo-Hsing Wen, Ya-Hui Chiu, Nien-Tzu Chou, Ching-Fang Lu, Cheng-Tai Chen, Ting-Shuo Chen, Pei-Shin Jiang
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Publication number: 20240103578Abstract: A control assembly configured for an electronic device, the control assembly includes a mount seat configured to be installed on the electronic device, two first connection components movably connected to the mount seat, two second connection component movably connected to the two first connection components, respectively, two controllers configured to communicate with the electronic device, the two controllers are separated apart from each other and movably connected to the second connection components, respectively, such that the two controllers are connected to the mount seat via the two second connection components and the two first connection components.Type: ApplicationFiled: November 25, 2022Publication date: March 28, 2024Applicant: DEXIN CORP.Inventors: Ho Lung LU, Chiu Tai CHANG, Min-Chien CHANG
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Publication number: 20240094282Abstract: A circuit test structure includes a chip including a conductive line which traces a perimeter of the chip. The circuit test structure further includes an interposer electrically connected to the chip, wherein the conductive line is over both the chip and the interposer. The circuit test structure further includes a test structure connected to the conductive line. The circuit test structure further includes a testing site, wherein the test structure is configured to electrically connect the testing site to the conductive line.Type: ApplicationFiled: November 22, 2023Publication date: March 21, 2024Inventors: Ching-Fang CHEN, Hsiang-Tai LU, Chih-Hsien LIN
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Publication number: 20240088124Abstract: A semiconductor structure, comprising a redistribution layer (RDL) including a dielectric layer and a conductive trace within the dielectric layer; a first conductive member disposed over the RDL and electrically connected with the conductive trace; a second conductive member disposed over the RDL and electrically connected with the conductive trace; a first die disposed over the RDL; a second die disposed over the first die, the first conductive member and the second conductive member; and a connector disposed between the second die and the second conductive member to electrically connect the second die with the conductive trace, wherein the first conductive member is electrically isolated from the second die.Type: ApplicationFiled: November 24, 2023Publication date: March 14, 2024Inventors: HSIANG-TAI LU, SHUO-MAO CHEN, MILL-JER WANG, FENG-CHENG HSU, CHAO-HSIANG YANG, SHIN-PUU JENG, CHENG-YI HONG, CHIH-HSIEN LIN, DAI-JANG CHEN, CHEN-HUA LIN
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Patent number: 11929125Abstract: Apparatuses and techniques are described for reducing the number of latches used in sense circuits for a memory device. The number of internal user data latches in a sense circuit is reduced by using an external data transfer latch to store a bit of user data, in place of an internal user data latch. The user data in the data transfer latches identifies a subset of the data states which are not prohibited from having a verify test. The subset is shifted as the program operation proceeds, at specified program loops, to encompass higher data states. The completion of programming by a memory cell is indicated by the user data latches and another internal latch of the sense circuit in place of the external data transfer latch.Type: GrantFiled: June 23, 2021Date of Patent: March 12, 2024Assignee: SanDisk Technologies LLCInventors: Tai-Yuan Tseng, Chia-Kai Chou, Iris Lu
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Patent number: 11915769Abstract: A non-volatile memory device includes a control circuit configured to connect to a bit line that is connected to one or more non-volatile memory cells. The control circuit includes a first plurality of data latches connected to a first local data bus to store first program-verify pass/fail bits and a second plurality of data latches connected to a second local data bus to store second program-verify pass/fail bits for second non-volatile memory cells. The non-volatile memory device further includes a shared isolation latch and one or more interface circuits connected to the first local data bus and the second local data bus. The one or more interface circuits are configured to selectively block the first program-verify pass/fail bits from the first plurality of latches and the second program-verify pass/fail bits from the second plurality of latches according to an indicator bit stored in the shared isolation latch.Type: GrantFiled: May 16, 2022Date of Patent: February 27, 2024Assignee: SanDisk Technologies LLCInventors: Kei Kitamura, Iris Lu, Tai-Yuan Tseng
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Publication number: 20240047384Abstract: A semiconductor device includes a first circuit area disposed over a substrate and enclosed by a first seal ring structure, a second circuit area disposed over the substrate and enclosed by a second seal ring structure, an internal scribe line disposed between the first circuit area and the second circuit area, and connecting seal structures connecting the first seal ring structure and the second seal ring structures such that a part of the first seal ring structure, a part of the second seal ring structure and the connecting seal structures enclose the internal scribe line.Type: ApplicationFiled: February 13, 2023Publication date: February 8, 2024Inventors: Chi-Hui LAI, Yang-Che CHEN, Hsiang-Tai LU, Wei-Ray LIN
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Patent number: 11855066Abstract: A method of manufacturing a semiconductor structure forming a redistribution layer (RDL); forming a conductive pad over the RDL; performing a first electrical test through the conductive pad; bonding a first die over the RDL by a connector; disposing a first underfill material to surround the connector; performing a second electrical test through the conductive pad; disposing a second die over the first die and the conductive pad; and disposing a second underfill material to surround the second die, wherein the conductive pad is at least partially in contact with the second underfill material, and is protruded from the RDL during the first electrical test and the second electrical test.Type: GrantFiled: May 13, 2022Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hsiang-Tai Lu, Shuo-Mao Chen, Mill-Jer Wang, Feng-Cheng Hsu, Chao-Hsiang Yang, Shin-Puu Jeng, Cheng-Yi Hong, Chih-Hsien Lin, Dai-Jang Chen, Chen-Hua Lin
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Publication number: 20230384013Abstract: A making device of ice balls comprises a refrigeration chamber unit; the refrigeration chamber unit comprises a lower half ball mold body, an upper half ball mold body and a water circulation unit; in addition, a cover plate is arranged above the refrigeration chamber unit, and a water injection hole is arranged on the cover plate; in addition, a plurality of low-temperature condensing tubes are arranged in the lower half ball mold body; in addition, the refrigeration chamber unit further comprises a thermo electric cooler, and a cold end face of the thermo electric cooler is attached to a bottom surface of the lower half ball mold body; the upper half ball mold body is arranged above the lower half ball mold body, a plurality of convection circulation holes are distributed on the upper half ball mold body, and a water inlet hole is arranged in the center of the upper half ball mold body; and the water circulation unit is arranged on the cover plate and comprises a pump, and the pump is respectively connectedType: ApplicationFiled: May 25, 2023Publication date: November 30, 2023Inventors: Xiang-Tai Lu, Shi-Jie Wang, Wei-Yuan Huang, Zhi-Xiang Dai, Jeff Chen
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Patent number: 11828790Abstract: A circuit test structure includes an interposer for electrically connecting to a chip, wherein the interposer includes a conductive line, and the conductive line extends along at least two side of the interposer. The circuit test structure further includes a plurality of electrical connections to the conductive line. The circuit test structure further includes a testing site electrically connected to the conductive line, wherein the testing site is on an opposite surface of the interposer from the plurality of electrical connections.Type: GrantFiled: April 13, 2021Date of Patent: November 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ching-Fang Chen, Hsiang-Tai Lu, Chih-Hsien Lin
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Publication number: 20230298970Abstract: A semiconductor structure includes a substrate, a capacitor disposed in the substrate, an interconnect structure disposed over the substrate, and a first doped region disposed in the substrate. The interconnect structure includes a first via structure coupled to the substrate, and a second via structure coupled to the capacitor. The first doped region is disposed under the first via structure. The first doped region includes p-type or n-type dopants.Type: ApplicationFiled: March 18, 2022Publication date: September 21, 2023Inventors: KUO WEN CHEN, HSIANG-TAI LU, CHIH-HSUAN TAI, MING-CHUNG WU
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Publication number: 20230238340Abstract: Semiconductor structures and methods of testing the same are provided. A semiconductor structure according to the present disclosure includes a substrate, a semiconductor device over the substrate, wherein the semiconductor device includes an interconnect structure, and the interconnect structure includes a plurality of metallization layers disposed in a dielectric layer; and a delamination sensor. The delamination sensor includes a connecting structure and a plurality of contact vias in at least one of the plurality of metallization layers. The connecting structure bonds the semiconductor device to the substrate and does not functionally couple the semiconductor device to the substrate. The plurality of contact vias fall within a first region of a vertical projection area of the connecting structure but do not overlap a second region of the vertical projection area.Type: ApplicationFiled: March 27, 2023Publication date: July 27, 2023Inventors: Chih-Hsuan Tai, Ming-Chung Wu, Kuo-Wen Chen, Hsiang-Tai Lu
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Patent number: 11616029Abstract: Semiconductor structures and methods of testing the same are provided. A semiconductor structure according to the present disclosure includes a substrate, a semiconductor device over the substrate, wherein the semiconductor device includes an interconnect structure, and the interconnect structure includes a plurality of metallization layers disposed in a dielectric layer; and a delamination sensor. The delamination sensor includes a connecting structure and a plurality of contact vias in at least one of the plurality of metallization layers. The connecting structure bonds the semiconductor device to the substrate and does not functionally couple the semiconductor device to the substrate. The plurality of contact vias fall within a first region of a vertical projection area of the connecting structure but do not overlap a second region of the vertical projection area.Type: GrantFiled: July 1, 2021Date of Patent: March 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Hsuan Tai, Ming-Chung Wu, Kuo-Wen Chen, Hsiang-Tai Lu
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Publication number: 20230087984Abstract: The invention provides a chemical-mechanical polishing composition comprising: (a) about 3.0 wt. % to about 10 wt. % silica abrasive; (b) an anionic polymer having a weight average molecular weight of about 400 kDa to about 7000 kDa; and (c) water, wherein the polishing composition has a viscosity of at least about 1 cPs, a ratio of viscosity (cPs) to wt. % of silica abrasive of about 0.2 cPs/wt. % to about 1.5 cPs/wt. %, and a pH of about 9 to about 12. The invention additional provides a chemical-mechanical polishing composition comprising: (a) about 3.0 wt. % to about 10 wt. % silica abrasive; (b) a nonionicpolymer having a weight average molecular weight of about 300 kDa to about 7000 kDa; and (c) water, wherein the polishing composition has a viscosity of at least about 2 cPs, and a pH of about 9 to about 12.Type: ApplicationFiled: September 23, 2022Publication date: March 23, 2023Inventors: Brian REISS, Brittany JOHNSON, Sajo NAIK, Lung-Tai LU, Kim LONG, Elliot KNAPTON, Douglas ROBELLO, Sarah BROSNAN
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Publication number: 20220375877Abstract: Semiconductor structures and methods of testing the same are provided. A semiconductor structure according to the present disclosure includes a substrate, a semiconductor device over the substrate, wherein the semiconductor device includes an interconnect structure, and the interconnect structure includes a plurality of metallization layers disposed in a dielectric layer; and a delamination sensor. The delamination sensor includes a connecting structure and a plurality of contact vias in at least one of the plurality of metallization layers. The connecting structure bonds the semiconductor device to the substrate and does not functionally couple the semiconductor device to the substrate. The plurality of contact vias fall within a first region of a vertical projection area of the connecting structure but do not overlap a second region of the vertical projection area.Type: ApplicationFiled: July 1, 2021Publication date: November 24, 2022Inventors: Chih-Hsuan Tai, Ming-Chung Wu, Kuo-Wen Chen, Hsiang-Tai Lu
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Publication number: 20220271024Abstract: A method of manufacturing a semiconductor structure forming a redistribution layer (RDL); forming a conductive pad over the RDL; performing a first electrical test through the conductive pad; bonding a first die over the RDL by a connector; disposing a first underfill material to surround the connector; performing a second electrical test through the conductive pad; disposing a second die over the first die and the conductive pad; and disposing a second underfill material to surround the second die, wherein the conductive pad is at least partially in contact with the second underfill material, and is protruded from the RDL during the first electrical test and the second electrical test.Type: ApplicationFiled: May 13, 2022Publication date: August 25, 2022Inventors: HSIANG-TAI LU, SHUO-MAO CHEN, MILL-JER WANG, FENG-CHENG HSU, CHAO-HSIANG YANG, SHIN-PUU JENG, CHENG-YI HONG, CHIH-HSIEN LIN, DAI-JANG CHEN, CHEN-HUA LIN
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Publication number: 20220243094Abstract: A chemical mechanical polishing composition for polishing a substrate including a silicon carbonitride layer, the composition comprising, consisting essentially of, or consisting of a water based liquid carrier, anionic colloidal silica particles dispersed in the liquid carrier, a topography control agent, and having a pH in a range from about 2 to about 7.Type: ApplicationFiled: February 4, 2022Publication date: August 4, 2022Inventors: Lung-Tai LU, Brian Reiss, Roman A. Ivanov
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Patent number: 11335672Abstract: A method of manufacturing a semiconductor structure forming a redistribution layer (RDL); forming a conductive pad over the RDL; performing a first electrical test through the conductive pad; bonding a first die over the RDL by a connector; disposing a first underfill material to surround the connector; performing a second electrical test through the conductive pad; disposing a second die over the first die and the conductive pad; and disposing a second underfill material to surround the second die, wherein the conductive pad is at least partially in contact with the second underfill material, and is protruded from the RDL during the first electrical test and the second electrical test.Type: GrantFiled: July 23, 2020Date of Patent: May 17, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hsiang-Tai Lu, Shuo-Mao Chen, Mill-Jer Wang, Feng-Cheng Hsu, Chao-Hsiang Yang, Shin-Puu Jeng, Cheng-Yi Hong, Chih-Hsien Lin, Dai-Jang Chen, Chen-Hua Lin
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Patent number: 11299929Abstract: A window blind includes a headrail, a covering assembly including a plurality of slats and a bottom rail, a lifting mechanism including a driving module and a lift cord assembly operably connected to the driving module, a tilt mechanism adapted to drive the slats to rotate, and an auxiliary unit provided between the tilt mechanism and the lifting mechanism. The lift cord assembly is connected to the bottom rail for expanding or folding the covering assembly. The covering assembly is in a first state when each and every one of the slats is substantially parallel to each other and correspondingly rotatable by the tilt mechanism, and is in a second state otherwise. When the covering assembly is in the second state, the auxiliary unit is drivable by the tilt mechanism to make the lifting mechanism further release the lift cord assembly, changing the covering assembly into the first state again.Type: GrantFiled: May 6, 2020Date of Patent: April 12, 2022Assignee: Nien Made Enterprise Co., Ltd.Inventors: Lin Chen, Chin-Tai Lu