Abstract: An electrical isolator packaging structure and a manufacturing method of an electrical isolator are provided. The electrical isolator packaging structure includes a first substrate, a second substrate, a coil, and a magnetic field (MF) sensor. The coil is disposed on the first substrate. The MF sensor is disposed on the second substrate. The position of the coil is arranged according to the position of the MF sensor such that the coil transmits a signal to the MF sensor. Thus, the electrical isolator can be implemented by magnetic coupling with the coil and the MF sensor.

Abstract: Technical solutions to automate alert remediation are described. One aspect includes a method that includes receiving a plurality of alerts from an application monitoring system, the plurality of alerts associated with a plurality of remediation procedures respectively. The method also includes selecting a subset of alerts from the plurality of alerts. The method also includes identifying a subset of remediation procedures corresponding to the subset of alerts and analyzing compliance, with a service level agreement, of an execution of the entire subset of remediation procedures. In response to the execution of the entire subset of remediation procedures being non-compliant, the latest alert that was added, is removed from the subset of alerts, and a remediation procedure corresponding to the latest alert is removed from the subset of remediation procedures. The method includes executing the entire subset of remediation procedures.

Abstract: The present invention generally relates to methods and friction-reducers for decreasing the friction of a fluid. More specifically, the method comprises contacting a friction-reducer to reduce the friction of a fluid flowing in a conduit. The friction-reducer comprises an emulsion polymer, comprising polyanion, polycation, and polynonionic monomers, and a highly concentrated salt solution.

Abstract: A non-volatile memory device including a non-volatile memory and a controller is provided. The non-volatile memory includes a plurality of closed blocks and a plurality of open blocks. The controller derives a ratio value according to the write workload of the non-volatile memory between a first time point and a second time point and then performs a patrol read on a portion of the closed blocks according to the ratio value.

Abstract: A personnel tracking and monitoring system and method comprises sets of monitoring devices each including: an electronic device having a unique identifier, a locating device, wireless communication devices communicating via a plurality of protocols, and an imaging device and a biologic monitor device communicating image and biologic data to the electronic device. The unique identifier, the location data and time data are associated with image data and with biologic data and are transmitted wirelessly via portable relay devices to one or more monitoring stations which store same in a database. Data stored in the data base is compared with predetermined criteria and if any predetermined criteria is exceeded, an indication thereof is communicated to the monitoring stations and/or to the electronic device to which such indication relates.

Abstract: An apparatus and method for outputting audio signals of a portable communication device are provided. The apparatus includes a plurality of audio tables including different volume control values or tone control values, and allows a user to selectively set audio tables corresponding to each of audio paths equipped with the portable communication device. Further, the apparatus analyzes a surrounding environment during a voice call, determines the absence or presence of noise, and suitably controls a volume or a tone of audio signals based on the result of the determination before outputting the audio signals. Accordingly, the apparatus can provide an improved calling condition in various calling environments.

Abstract: A driving circuit and a pin output order arranging method are disclosed. The driving circuit includes (M*N) pins and an arranging module. A first pin˜an N-th pin of the (M*N) pins, a (N+1)-th pin˜an 2N-th pin of the (M*N) pins, . . . , a [(M?1)*N+1]-th pin˜a (M*N)-th pin of the (M*N) pins are arranged along a first direction in a specific distance spaced to form a first row of pins˜an M-th row of pins. The first row of pins˜the M-th row of pins are staggered along a second direction in a staggering way or an aligning way. M and N are integers larger than 1. The arranging module correspondingly arranges the pin output order of the (M*N) pins according to different application modes of the driving circuit.

Abstract: The present invention relates to a substrate with a crystallized silicon film and manufacturing method thereof, wherein the substrate with the crystallized silicon film comprises: a substrate, which is a polymer substrate; and a crystallized silicon film, which is formed on at least one surface of the substrate, wherein the crystallized silicon film comprises a plurality of silicon crystals with column structures, and the crystallinity of the crystallized silicon film is higher than 90%.

Abstract: Provided herein are isotopically enriched arylsulfonamides, for example, of Formula I, that are useful for modulating CCR3 activity, and pharmaceutical compositions thereof. Also provided herein are methods of their use for treating, preventing, or ameliorating one or more symptoms of a CCR3-mediated disease, disorder, or condition.

Abstract: A semiconductor device is made by providing a sacrificial substrate and depositing an adhesive layer over the sacrificial substrate. A first conductive layer is formed over the adhesive layer. A polymer pillar is formed over the first conductive layer. A second conductive layer is formed over the polymer pillar to create a conductive pillar with inner polymer core. A semiconductor die or component is mounted over the substrate. An encapsulant is deposited over the semiconductor die or component and around the conductive pillar. A first interconnect structure is formed over a first side of the encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The sacrificial substrate and adhesive layers are removed. A second interconnect structure is formed over a second side of the encapsulant opposite the first interconnect structure. The second interconnect structure is electrically connected to the conductive pillar.

Abstract: An electronic device is provided. The electronic device includes a reception unit configured to receive an audio signal, a bandwidth change unit configured to gradually change a bandwidth of the received audio signal from a first bandwidth to a second bandwidth during a preset time, when the received audio signal is changed, and an audio output unit configured to output the received audio signal.

Abstract: A high-voltage FinFET device having LDMOS structure and a method for manufacturing the same are provided. The high-voltage FinFET device includes: at least one fin structure, a working gate, a shallow trench isolation structure, and a first dummy gate. The fin structure includes a first-type well region and a second-type well region adjacent to the first-type well region, and further includes a first part and a second part. A trench is disposed between the first part and the second part and disposed in the first-type well region. A drain doped layer is disposed on the first part which is disposed in the first-type well region, and a source doped layer is disposed on the second part which is disposed in the second-type well region. The working gate is disposed on the fin structure which is disposed in the first-type well region and in the second-type well region.

Abstract: A housing includes a main portion and at least one insulating portion. The main portion includes two portions, an inner surface and an outer surface opposite to the inner surface. The inner surface defines at least one groove. The outer surface defines at least one gap that is coupled to the at least one groove. The at least one insulating portion is corresponding to the at least one groove and each insulating portion is filled in one groove. The two portions of the main portion are positioned at two sides of the at least one gap and the two portions are insulated by the at least one gap and the at least one insulating portion.

Abstract: Various embodiments provide an optical image stabilization circuit that synchronizes its gyroscope and drive circuit using gyroscope data ready signals and gyroscope reset signals. In response to a gyroscope data ready signal, the optical image stabilization circuit synchronously obtains position measurements of a camera lens when power drive signals are not transitioning from one power level to another power level, and synchronously transitions the power drive signals simultaneously with gyroscope reset signals. By synchronizing the gyroscope and the drive circuit, the gyroscope and other onboard sensing circuits are isolated from noise generated by the drive circuit.

Abstract: An apparatus includes a first bit line coupled to a first storage element and a second bit line coupled to a second storage element. A first bit line charging circuit is coupled to the first bit line and is configured to charge the first bit line to a first bias voltage of multiple bias voltages based on a first programming state. A second bit line charging circuit is coupled to the second bit line and is configured to charge the second bit line to a second bias voltage of the multiple bias voltages based on a second programming state. The second programming state is different than the first programming state.

Abstract: An integrated power module packaging structure includes a housing, a first circuit board, a second circuit board, a first pin, a second pin and a third pin. The housing has a cavity. The second circuit board is located above the first circuit board, and both them are received in the cavity. A switching module is disposed on the first circuit board. A high side current/voltage detecting device and a driving device are disposed on the second circuit board. The first pin, the second pin and the third pin are disposed between the first circuit board and the second circuit board. The first pin connects the high side current/voltage detecting device and the switching module in series. The second pin connects the switching module. The driving device controls the switching module through the third pin.

Abstract: A hybridized CMP conditioner includes a base, a first abrasive unit and a plurality of second abrasive units. The first abrasive unit includes a first bonding layer, a substrate for abrasive unit provided on the first bonding layer and an abrasive layer provided on the substrate for abrasive unit. The abrasive layer is a diamond coating. The diamond coating is provided on the surface thereof with a plurality of abrasive tips. Each second abrasive unit includes a second bonding layer, a carrying post provided on the second bonding layer, an abrasive particle provided on the carrying post and an abrasive material-bonding layer provided between the carrying post and the abrasive particle. The CMP conditioner is provided with both excellent cutting force and flattening capability through the first abrasive unit provided with the abrasive layer and the second abrasive units provided with the abrasive particles.

Abstract: A data line driving circuit for a display device having a plurality of data lines is provided to include a plurality of data line drivers respectively coupled to the data lines. Each data line driver includes a register unit to store video data having a pixel value, a pulse width modulation unit generating a PWM signal having a pulse width positively correlated with the pixel value, and a charge-discharge unit performing charge-discharge operation to generate a data voltage on a respective one of the data lines according to the PWM signal. A magnitude of voltage variation on the respective data line is positively correlated with the pulse width of the PWM signal during the charge-discharge operation.

Abstract: Apparatus, system, and method of depositing thin and ultra-thin parylene are described. In an example, a core deposition chamber is used. The core deposition chamber includes a base and a rigid, removable cover configured to mate and seal with the base to create the core deposition chamber and to define an inside and an outside of the core deposition chamber. The core deposition chamber also includes a conduit through a top of the cover. The conduit has a lumen connecting the inside to the outside of the core deposition chamber. The lumen has a length and a cross-section. The cross-section has a width between 50 ?m and 6000 ?m. The length is less than 140 times the cross-section width. The core deposition chamber can be placed in an outer deposition chamber and can achieve parylene deposition less than 1 ?m thick inside the core deposition chamber.

Abstract: Techniques are disclosed relating to self-addressing memory. In one embodiment, an apparatus includes a memory and addressing circuitry coupled to or comprised in the memory. In this embodiment, the addressing circuitry is configured to receive memory access requests corresponding to a specified sequence of memory accesses. In this embodiment, the memory access requests do not include address information. In this embodiment, the addressing circuitry is further configured to assign addresses to the memory access requests for the specified sequence of memory accesses. In some embodiments, the apparatus is configured to perform the memory access requests using the assigned addresses.