Patents by Inventor Tai-Bor Wu
Tai-Bor Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9711373Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a substrate, forming an interfacial layer on the substrate by treating the substrate with radicals, and forming a high-k dielectric layer on the interfacial layer. The radicals are selected from the group consisting of hydrous radicals, nitrogen/hydrogen radicals, and sulfur/hydrogen radicals.Type: GrantFiled: August 31, 2009Date of Patent: July 18, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Che-Hao Chang, Cheng-Hao Hou, Chen-Hua Yu, Tai-Bor Wu
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Publication number: 20110011148Abstract: A method for forming a patterned modified metal layer is disclosed, which comprises the following steps: (A) providing a metal base which is in the form of either a bulk metal or a metal coated substrate, and a mold with patterns; (B) applying the mold onto the metal base to transfer the patterns of the mold to the metal surface; (C) removing the mold; and (D) modifying the whole metal base or the, surface and a certain depth beneath the surface of metal base to form a modified metal layer with designated patterns.Type: ApplicationFiled: September 23, 2009Publication date: January 20, 2011Applicant: National Tsing Hua UniversityInventors: Sun-Zen Chen, Tai-Bor Wu, Ching-Wen Chang, Wen-Feng Kuo, Ruo-Ying Wu
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Publication number: 20100093184Abstract: A method for making a metal oxide layer includes: (a) exposing a substrate having oxygen-containing reaction sites to an environment of a first precursor of an organometallic compound, which contains a metal atom and ligand groups, so as to form a chemisorption layer of the first precursor on the substrate; (b) exposing the chemisorption layer on the substrate to a non-free radical environment of a second precursor after step (a) so as to remove the ligand groups of the chemisorption layer that are unreacted in step (a) and so as to convert the chemisorption layer into a metal oxide layer; and (c) after step (b), exposing the metal oxide layer on the substrate to a free radical-containing gas containing free radicals so as to remove the ligand groups of the chemisorption layer that are left unreacted in step (b).Type: ApplicationFiled: October 14, 2009Publication date: April 15, 2010Applicant: NATIONAL TSING HUA UNIVERSITYInventors: Tai-Bor Wu, Cheng-Hao Hou
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Publication number: 20100075507Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a substrate, forming an interfacial layer on the substrate by treating the substrate with radicals, and forming a high-k dielectric layer on the interfacial layer. The radicals are selected from the group consisting of hydrous radicals, nitrogen/hydrogen radicals, and sulfur/hydrogen radicals.Type: ApplicationFiled: August 31, 2009Publication date: March 25, 2010Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Che-Hao Chang, Cheng-Hao Hou, Chen-Hua Yu, Tai-Bor Wu
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Patent number: 7579612Abstract: Disclosed herein are new resistive memory devices having one or more buffers layer surrounding a dielectric layer. By inserting one or more buffer layers around the dielectric layer of the device, the resistive ratio of the device is highly enhanced. For example, tests using this unique stack structure have revealed a resistance ratio of approximately 1000× over conventional electrode-dielectric-electrode stack structures found in resistive memory devices. This improvement in the resistance ratio of the resistive memory device is believed to be from the improved interface coherence, and thus smoother topography, between the buffer layer(s) and the dielectric layer.Type: GrantFiled: April 25, 2007Date of Patent: August 25, 2009Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Denny Tang, Tai-Bor Wu, Wen-Yuan Chang, Tzyh-Cheang Lee
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Publication number: 20080266931Abstract: Disclosed herein are new resistive memory devices having one or more buffers layer surrounding a dielectric layer. By inserting one or more buffer layers around the dielectric layer of the device, the resistive ratio of the device is highly enhanced. For example, tests using this unique stack structure have revealed a resistance ratio of approximately 1000× over conventional electrode-dielectric-electrode stack structures found in resistive memory devices. This improvement in the resistance ratio of the resistive memory device is believed to be from the improved interface coherence, and thus smoother topography, between the buffer layer(s) and the dielectric layer.Type: ApplicationFiled: April 25, 2007Publication date: October 30, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Denny Tang, Tai-Bor Wu, Wen-Yuan Chang, Tzyh-Cheang Lee
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Patent number: 7332760Abstract: A ferroelectric material includes a superlattice structure having lead zirconate layers and barium zirconate layers such that the superlattice structure has remanent polarization exhibiting a linearly positive dependency on a driving voltage.Type: GrantFiled: June 24, 2005Date of Patent: February 19, 2008Assignee: National Tsing Hua UniversityInventors: Tai-Bor Wu, Cheng-Lung Hung
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Patent number: 7307304Abstract: A ferroelectric material includes a compound of formula (I): (Pb1?x?zBazAx)(ByZr1?y)O3, ??(I) wherein 0?x?0.1, 0?y?0.020, 0.15?z?0.35, with the proviso that y?0 when x=0, and that x?0, when y=0; and wherein A is a first element having a valence number greater than that of Pb, and B is a second element having a valence number greater than that of Zr. A ferroelectric memory device made from the ferroelectric material is also disclosed.Type: GrantFiled: June 9, 2005Date of Patent: December 11, 2007Assignee: National Tsing Hua UniversityInventors: Tai-Bor Wu, Cheng-Lung Hung
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Publication number: 20070012977Abstract: A semiconductor device includes a MOS transistor having a capacitor-forming surface; and a ferroelectric capacitor formed on the capacitor-forming surface of the MOS transistor and including upper and lower electrode layers of Pt and a dielectric layer sandwiched between the upper and lower electrode layers. The ferroelectric capacitor has a cross-section that is generally trapezoid in shape, and that has an inclined side which forms an angle of greater than 45 degrees and less than 90 degrees with the capacitor-forming surface of the MOS transistor.Type: ApplicationFiled: September 18, 2006Publication date: January 18, 2007Inventors: Tai-Bor Wu, Chun-Kai Huang
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Patent number: 7071007Abstract: A method of forming a low-voltage drive thin film ferroelectric capacitor includes the steps of depositing a ferroelectric and platinum thin film dielectric layer over a bottom electrode, annealing the dielectric layer, wherein a nanocomposite layer is formed including nanoparticles of platinum and forming a top electrode over the dielectric layer. An integrated circuit is also provided including a ferroelectric capacitor. The capacitor includes a bottom electrode formed over a substrate and a ferroelectric and platinum thin film nanocomposite dielectric layer formed over the bottom electrode, wherein the nanocomposite layer includes nanoparticles of platinum. A top electrode is formed over the dielectric layer.Type: GrantFiled: December 6, 2002Date of Patent: July 4, 2006Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yuan-Chieh Tseng, Chao-Hsiung Wang, Tai-Bor Wu
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Publication number: 20060038214Abstract: A method of forming a low-voltage drive thin film ferroelectric capacitor includes the steps of depositing a ferroelectric and platinum thin film dielectric layer over a bottom electrode, annealing the dielectric layer, wherein a nanocomposite layer is formed including nanoparticles of platinum and forming a top electrode over the dielectric layer. An integrated circuit is also provided including a ferroelectric capacitor. The capacitor includes a bottom electrode formed over a substrate and a ferroelectric and platinum thin film nanocomposite dielectric layer formed over the bottom electrode, wherein the nanocomposite layer includes nanoparticles of platinum. A top electrode is formed over the dielectric layer.Type: ApplicationFiled: October 18, 2005Publication date: February 23, 2006Inventors: Yuan-Chieh Tseng, Chao-Hsiung Wang, Tai-Bor Wu
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Publication number: 20050286290Abstract: A ferroelectric material includes a superlattice structure having lead zirconate layers and barium zirconate layers such that the superlattice structure has remanent polarization exhibiting a linearly positive dependency on a driving voltage.Type: ApplicationFiled: June 24, 2005Publication date: December 29, 2005Inventors: Tai-Bor Wu, Cheng-Lung Hung
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Publication number: 20050285171Abstract: A ferroelectric material includes a compound of formula (I): (Pb1-x-zBazAx) (ByZr1-y)O3??(I) wherein 0?x?0.1, 0?y?0.020, 0.15?z?0.35, with the proviso that y?0 when x=0, and that x?0, when y=0; and wherein A is a first element having a valence number greater than that of Pb, and B is a second element having a valence number greater than that of Zr. A ferroelectric memory device made from the ferroelectric material is also disclosed.Type: ApplicationFiled: June 9, 2005Publication date: December 29, 2005Inventors: Tai-Bor Wu, Cheng-Lung Hung
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Publication number: 20050263807Abstract: A semiconductor device includes a MOS transistor, and a ferroelectric capacitor formed on the MOS transistor and including upper and lower electrode layers and a dielectric layer sandwiched between the upper and lower electrode layers. Each of the upper and lower electrode layers is made from a Pt—PtOx material, in which x is an integer from 1 to 2, and the weight percentage of PtOx based on the total weight of the Pt—PtOx material is in an amount ranging from 50-100%.Type: ApplicationFiled: April 11, 2005Publication date: December 1, 2005Inventors: Tai-Bor Wu, Chun-Kai Huang
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Patent number: 6927136Abstract: A non-volatile memory cell is described. The non-volatile memory cell comprises a substrate, a charge-trapping layer, a gate and a source/drain. The charge-trapping layer comprises an insulating layer and metal nano-particles contained therein, wherein the metal nano-particles are formed with thermal dissociation of an oxide of the same metal. The gate is disposed on the charge-trapping layer, and the source/drain is located in the substrate beside the gate.Type: GrantFiled: August 25, 2003Date of Patent: August 9, 2005Assignee: Macronix International Co., Ltd.Inventors: Hsiang-Lan Lung, Kuang-Yeu Hsieh, Ruichen Liu, Tai-Bor Wu, Jiun-Yi Tseng
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Publication number: 20050045943Abstract: A non-volatile memory cell is described. The non-volatile memory cell comprises a substrate, a charge-trapping layer, a gate and a source/drain. The charge-trapping layer comprises an insulating layer and metal nano-particles contained therein, wherein the metal nano-particles are formed with thermal dissociation of an oxide of the same metal. The gate is disposed on the charge-trapping layer, and the source/drain is located in the substrate beside the gate.Type: ApplicationFiled: August 25, 2003Publication date: March 3, 2005Inventors: Hsiang-Lan Lung, Kuang-Yeu Hsieh, Ruichen Liu, Tai-Bor Wu, Jiun-Yi Tseng
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Publication number: 20040110309Abstract: A method of forming a low-voltage drive thin film ferroelectric capacitor includes the steps of depositing a ferroelectric and platinum thin film dielectric layer over a bottom electrode, annealing the dielectric layer, wherein a nanocomposite layer is formed including nanoparticles of platinum and forming a top electrode over the dielectric layer. An integrated circuit is also provided including a ferroelectric capacitor. The capacitor includes a bottom electrode formed over a substrate and a ferroelectric and platinum thin film nanocomposite dielectric layer formed over the bottom electrode, wherein the nanocomposite layer includes nanoparticles of platinum. A top electrode is formed over the dielectric layer.Type: ApplicationFiled: December 6, 2002Publication date: June 10, 2004Inventors: Yuan-Chieh Tseng, Chao-Hsiung Wang, Tai-Bor Wu
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Patent number: 6640403Abstract: A method for forming a dielectric-constant-enhanced capacitor is provided. A wafer in a reaction chamber is provided, wherein said wafer comprises a first conductive layer. Then, a first dielectric layer is formed above said first conductive layer to prevent said first conductive layer from growing silicon oxide and to diminish leakage current. Next a precursor is transmitted to a vaporizer. Then said precursor is transformed to a gas and said gas is transmitted to said reaction chamber. Next, a second dielectric layer is deposited above said first dielectric layer. Then a heat treatment is proceeded and a second conductive layer is formed on said second dielectric layer.Type: GrantFiled: May 29, 2001Date of Patent: November 4, 2003Assignee: Vanguard International Semiconductor CorporationInventors: Wong-Cheng Shih, Lan Lin Chao, Tai-Bor Wu, Chich-Shang Chang
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Patent number: 6559497Abstract: Within a method for fabricating a capacitor structure and a capacitor structure fabricated employing the method, there is provided a conductor barrier layer formed upon an upper capacitor plate formed within the capacitor structure. There is also provided a silicon layer formed upon the conductor barrier layer. The conductor barrier layer and the silicon layer provide for enhanced interdiffusion stability and enhanced delamination stability with respect to the upper capacitor plate, and thus enhanced reliability and performance of the capacitor structure.Type: GrantFiled: September 6, 2001Date of Patent: May 6, 2003Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wong-Cheng Shih, Tai Bor Wu, Chich Shang Chang
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Publication number: 20030047770Abstract: Within a method for fabricating a capacitor structure and a capacitor structure fabricated employing the method, there is provided a conductor barrier layer formed upon an upper capacitor plate formed within the capacitor structure. There is also provided a silicon layer formed upon the conductor barrier layer. The conductor barrier layer and the silicon layer provide for enhanced interdiffusion stability and enhanced delamination stability with respect to the upper capacitor plate, and thus enhanced reliability and performance of the capacitor structure.Type: ApplicationFiled: September 6, 2001Publication date: March 13, 2003Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wong-Cheng Shih, Tai Bor Wu, Chich Shang Chang