Patents by Inventor Tai Chan
Tai Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11960268Abstract: Examples discussed herein relate to managing power allocation for devices, such as network devices, with processing chip. In some examples, based on determining that a first temperature measurement of the processing chip does not satisfy an operating temperature threshold, the network device allocates power from a power source to a first heating element of the network device to heat the processing chip & allocates power from the power source to a second heating element of the network device to heat the processing chip. Based on determining that a second temperature measurement satisfies the operating temperature threshold, the network device allocates power from the power source to a set of power over ethernet ports of the network device & the first amount of power from the power source selectively to the first heating element to heat the processing chip.Type: GrantFiled: May 4, 2021Date of Patent: April 16, 2024Assignee: Hewlett Packard Enterprise Development LPInventors: Khai Chiah Chng, Mun Hoong Tai, Kum Cheong Adam Chan, Song Poh Chai
-
Patent number: 11935954Abstract: A semiconductor device structure includes a fin structure formed over a substrate. The structure also includes nanostructures formed over the fin structure. The structure also includes a gate structure wrapped around the nanostructures. The structure also includes a first inner spacer formed beside the gate structure. The structure also includes a second inner spacer formed beside the first inner spacer. The structure also includes spacer layers formed over opposite sides of the gate structure above the nanostructures. The structure also includes source/drain epitaxial structures formed over opposite sides of the fin structure. The second inner spacer is partially embedded in the source/drain epitaxial structures.Type: GrantFiled: July 30, 2021Date of Patent: March 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Bwo-Ning Chen, Xusheng Wu, Chang-Miao Liu, Chien-Tai Chan
-
Publication number: 20230378268Abstract: A semiconductor device structure and a formation method are provided. The method includes forming a protruding structure over a substrate. The protruding structure has multiple sacrificial layers and multiple semiconductor layers, and the sacrificial layers and the semiconductor layers have an alternating configuration. The method also includes forming a gate stack to wrap a portion of the protruding structure. The method further includes forming an epitaxial structure abutting edges of the semiconductor layers. The formation of the epitaxial structure includes forming a lower semiconductor portion on a bottom of the recess and forming an upper semiconductor portion over the lower semiconductor portion. The upper semiconductor portion and the lower semiconductor portion are oppositely doped.Type: ApplicationFiled: May 17, 2022Publication date: November 23, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Tai CHAN, Yu-Ching HUANG, Chien-Chih LIN, Hsueh-Jen YANG
-
Publication number: 20230088366Abstract: A light-transmitting display panel, a manufacturing method thereof and a display device. The light-transmitting display panel includes a substrate and a light-emitting device layer disposed on the substrate, the light-emitting device layer including a plurality of pixel units and a shielding layer with a plurality of openings, each of the pixel units disposed correspondingly in one of the openings, and each pixel unit including a transparent light transmission portion and a plurality of sub-pixels emitting light of at least three colors distributed around the transparent light transmission portion.Type: ApplicationFiled: November 21, 2022Publication date: March 23, 2023Applicant: Hefei Visionox Technology Co., Ltd.Inventor: Huang-Tai CHAN
-
Publication number: 20230035791Abstract: A semiconductor device structure includes a fin structure formed over a substrate. The structure also includes nanostructures formed over the fin structure. The structure also includes a gate structure wrapped around the nanostructures. The structure also includes a first inner spacer formed beside the gate structure. The structure also includes a second inner spacer formed beside the first inner spacer. The structure also includes spacer layers formed over opposite sides of the gate structure above the nanostructures. The structure also includes source/drain epitaxial structures formed over opposite sides of the fin structure. The second inner spacer is partially embedded in the source/drain epitaxial structures.Type: ApplicationFiled: July 30, 2021Publication date: February 2, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bwo-Ning CHEN, Xusheng WU, Chang-Miao LIU, Chien-Tai CHAN
-
Publication number: 20220336644Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first fin structure with a first height and a first width formed over the substrate, a second fin structure with a second height and a second width formed over the substrate, and an insulating stack formed over lower portions of the first and second fin structures. The second height can be substantially equal to the first height and the second width can be greater than the first width. A top surface of the insulating stack can be below top surfaces of the first and second fin structures.Type: ApplicationFiled: June 30, 2022Publication date: October 20, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Su-Hao Liu, Huicheng Chang, Chien-Tai Chan, Liang-Yin Chen, Yee-Chia Yeo, Szu-Ying Chen
-
Patent number: 11380782Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first fin structure with a first height and a first width formed over the substrate, a second fin structure with a second height and a second width formed over the substrate, and an insulating stack formed over lower portions of the first and second fin structures. The second height can be substantially equal to the first height and the second width can be greater than the first width. A top surface of the insulating stack can be below top surfaces of the first and second fin structures.Type: GrantFiled: August 18, 2020Date of Patent: July 5, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Su-Hao Liu, Huicheng Chang, Chien-Tai Chan, Liang-Yin Chen, Yee-Chia Yeo, Szu-Ying Chen
-
Publication number: 20220059679Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first fin structure with a first height and a first width formed over the substrate, a second fin structure with a second height and a second width formed over the substrate, and an insulating stack formed over lower portions of the first and second fin structures. The second height can be substantially equal to the first height and the second width can be greater than the first width. A top surface of the insulating stack can be below top surfaces of the first and second fin structures.Type: ApplicationFiled: August 18, 2020Publication date: February 24, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Su-Hao LIU, Huicheng CHANG, Chien-Tai CHAN, Liang-Yin CHEN, Yee-Chia YEO, Szu-Ying CHEN
-
Patent number: 11227951Abstract: A FinFET device and a method of forming the same are disclosed. In accordance with some embodiments, a FinFET device includes a substrate having at least one fin, a gate stack across the at least one fin, a strained layer aside the gate stack and a silicide layer over the strained layer. The strained layer has a boron surface concentration greater than about 2E20 atom/cm3 within a depth range of about 0-5 nm from a surface of the strained layer.Type: GrantFiled: May 19, 2020Date of Patent: January 18, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Hsiung Tsai, Chien-Tai Chan, Ziwei Fang, Kei-Wei Chen, Huai-Tei Yang
-
Patent number: 11211455Abstract: Embodiments of mechanisms for forming dislocations in source and drain regions of finFET devices are provided. The mechanisms involve recessing fins and removing the dielectric material in the isolation structures neighboring fins to increase epitaxial regions for dislocation formation. The mechanisms also involve performing a pre-amorphous implantation (PAI) process either before or after the epitaxial growth in the recessed source and drain regions. An anneal process after the PAI process enables consistent growth of the dislocations in the source and drain regions. The dislocations in the source and drain regions (or stressor regions) can form consistently to produce targeted strain in the source and drain regions to improve carrier mobility and device performance for NMOS devices.Type: GrantFiled: July 20, 2020Date of Patent: December 28, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun Hsiung Tsai, Wei-Yuan Lu, Chien-Tai Chan, Wei-Yang Lee, Da-Wen Lin
-
Patent number: 11195931Abstract: A gate structure, a semiconductor device, and the method of forming a semiconductor device are provided. In various embodiments, the gate structure includes a gate stack and a doped spacer overlying a sidewall of the gate stack. The gate stack contains a doped work function metal (WFM) stack and a metal gate electrode overlying the doped WFM stack.Type: GrantFiled: August 17, 2020Date of Patent: December 7, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Hsiung Tsai, Kuo-Feng Yu, Chien-Tai Chan, Ziwei Fang, Kei-Wei Chen, Huai-Tei Yang
-
Publication number: 20200381529Abstract: A gate structure, a semiconductor device, and the method of forming a semiconductor device are provided. In various embodiments, the gate structure includes a gate stack and a doped spacer overlying a sidewall of the gate stack. The gate stack contains a doped work function metal (WFM) stack and a metal gate electrode overlying the doped WFM stack.Type: ApplicationFiled: August 17, 2020Publication date: December 3, 2020Inventors: Chun-Hsiung Tsai, Kuo-Feng Yu, Chien-Tai Chan, Ziwei Fang, Kei-Wei Chen, Huai-Tei Yang
-
Publication number: 20200350404Abstract: Embodiments of mechanisms for forming dislocations in source and drain regions of finFET devices are provided. The mechanisms involve recessing fins and removing the dielectric material in the isolation structures neighboring fins to increase epitaxial regions for dislocation formation. The mechanisms also involve performing a pre-amorphous implantation (PAI) process either before or after the epitaxial growth in the recessed source and drain regions. An anneal process after the PAI process enables consistent growth of the dislocations in the source and drain regions. The dislocations in the source and drain regions (or stressor regions) can form consistently to produce targeted strain in the source and drain regions to improve carrier mobility and device performance for NMOS devices.Type: ApplicationFiled: July 20, 2020Publication date: November 5, 2020Inventors: Chun Hsiung Tsai, Wei-Yuan Lu, Chien-Tai Chan, Wei-Yang Lee, Da-Wen Lin
-
Publication number: 20200279949Abstract: A FinFET device and a method of forming the same are disclosed. In accordance with some embodiments, a FinFET device includes a substrate having at least one fin, a gate stack across the at least one fin, a strained layer aside the gate stack and a silicide layer over the strained layer. The strained layer has a boron surface concentration greater than about 2E20 atom/cm3 within a depth range of about 0-5 nm from a surface of the strained layer.Type: ApplicationFiled: May 19, 2020Publication date: September 3, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Hsiung Tsai, Chien-Tai Chan, Ziwei Fang, Kei-Wei Chen, Huai-Tei Yang
-
Patent number: 10749008Abstract: A gate structure, a semiconductor device, and the method of forming a semiconductor device are provided. In various embodiments, the gate structure includes a gate stack and a doped spacer overlying a sidewall of the gate stack. The gate stack contains a doped work function metal (WFM) stack and a metal gate electrode overlying the doped WFM stack.Type: GrantFiled: July 31, 2018Date of Patent: August 18, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Hsiung Tsai, Kuo-Feng Yu, Chien-Tai Chan, Ziwei Fang, Kei-Wei Chen, Huai-Tei Yang
-
Patent number: 10741642Abstract: Embodiments of mechanisms for forming dislocations in source and drain regions of finFET devices are provided. The mechanisms involve recessing fins and removing the dielectric material in the isolation structures neighboring fins to increase epitaxial regions for dislocation formation. The mechanisms also involve performing a pre-amorphous implantation (PAI) process either before or after the epitaxial growth in the recessed source and drain regions. An anneal process after the PAI process enables consistent growth of the dislocations in the source and drain regions. The dislocations in the source and drain regions (or stressor regions) can form consistently to produce targeted strain in the source and drain regions to improve carrier mobility and device performance for NMOS devices.Type: GrantFiled: December 5, 2018Date of Patent: August 11, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun Hsiung Tsai, Wei-Yuan Lu, Chien-Tai Chan, Wei-Yang Lee, Da-Wen Lin
-
Patent number: 10665717Abstract: A FinFET device and a method of forming the same are disclosed. In accordance with some embodiments, a FinFET device includes a substrate having at least one fin, a gate stack across the at least one fin, a strained layer aside the gate stack and a silicide layer over the strained layer. The strained layer has a boron surface concentration greater than about 2E20 atom/cm3 within a depth range of about 0-5 nm from a surface of the strained layer.Type: GrantFiled: August 26, 2018Date of Patent: May 26, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun Hsiung Tsai, Chien-Tai Chan, Ziwei Fang, Kei-Wei Chen, Huai-Tei Yang
-
Patent number: 10515856Abstract: A method includes forming first and second fins of a finFET extending above a semiconductor substrate, with a shallow trench isolation (STI) region in between, and a distance between a top surface of the STI region and top surfaces of the first and second fins. First and second fin extensions are provided on top and side surfaces of the first and second fins above the top surface of the STI region. Material is removed from the STI region, to increase the distance between the top surface of the STI region and top surfaces of the first and second fins. A conformal stressor dielectric material is deposited over the fins and STI region. The conformal dielectric stressor material is reflowed, to flow into a space between the first and second fins above a top surface of the STI region, to apply stress to a channel of the finFET.Type: GrantFiled: February 8, 2019Date of Patent: December 24, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Pin Linus Lin, Chien-Tai Chan, Hsien-Chin Lin, Shyue-Shyh Lin
-
Patent number: 10504898Abstract: A fin field-effect transistor (FinFET) structure and a method for forming the same are provided. The FinFET structure includes a first fin structure that protrudes from a first region of a substrate. A second fin structure protrudes from a second region of the substrate. Isolation regions cover lower portions of the first fin structure and the second fin structure and leave upper portions of the first fin structure and the second fin structure above the isolation regions. A first liner layer is positioned between the lower portion of the first fin structure and the isolation regions in the first region. A second liner layer covers the lower portion of the second fin structure and is positioned between the second fin structure and the isolation regions in the second region. The first liner layer and the second liner layer are formed of different materials.Type: GrantFiled: August 28, 2017Date of Patent: December 10, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yin Wang, Chien-Chih Lin, Chien-Tai Chan, Wei-Ken Lin, Chun-Te Li
-
Publication number: 20190181048Abstract: A method includes forming first and second fins of a finFET extending above a semiconductor substrate, with a shallow trench isolation (STI) region in between, and a distance between a top surface of the STI region and top surfaces of the first and second fins. First and second fin extensions are provided on top and side surfaces of the first and second fins above the top surface of the STI region. Material is removed from the STI region, to increase the distance between the top surface of the STI region and top surfaces of the first and second fins. A conformal stressor dielectric material is deposited over the fins and STI region. The conformal dielectric stressor material is reflowed, to flow into a space between the first and second fins above a top surface of the STI region, to apply stress to a channel of the finFET.Type: ApplicationFiled: February 8, 2019Publication date: June 13, 2019Inventors: Chia-Pin LIN, Chien-Tai CHAN, Hsien-Chin LIN, Shyue-Shyh LIN