Abstract: A processing system comprises a digital signal processor (DSP) device and a host system on which the DSP device is implemented. The DSP device comprises a shared program memory and a plurality of processor subsystems coupled to the shared program memory to concurrently execute program instructions stored in the shared program memory. The host system is capable of independently debugging each subsystem. During debugging, the host device inserts breakpoints into the shared program memory and tracks the debug breakpoints to determine which subsystems are associated with the breakpoints. When a subsystem executes a breakpoint associated with that subsystem, the subsystem halts until the host gathers necessary debug information from the subsystem. However, when a subsystem executes a breakpoint that is not associated with that subsystem, the host system causes the subsystem to execute the original program instructions and proceed as directed.

Abstract: A digital signal processing system includes multiple processor subsystems, an external input/output port (XPORT), and an XPORT arbiter. The processor subsystems each include a processor core and a DMA controller. The XPORT arbiter arbitrates between the processor cores and between the DMA controllers, and further arbitrates between processor control or DMA control of the XPORT. Upon a request signal from a DMA controller, the XPORT arbiter asserts a hold signal to the processor cores. The processor cores respond by asserting a hold acknowledge signal. A processor core will delay the hold acknowledge signal until through with the XPORT. The arbiter, then asserts a grant signal to the DMA controller requesting access. The arbiter may assert a grant signal to a processor core requesting access. However, the processor core's access will be stalled as long as the hold signal is asserted.

Abstract: A digital signal processing chip having a multiple processor cores with corresponding processor subsystems, a shared component, and a clock tree, is disclosed herein. A clock tree distributes clock signals to the processor cores and the shared component. The clock tree can be configured to disable one or more of the processor cores and the shared component by blocking the corresponding clock signal. This may advantageously conserve power. However, the clock tree is configured to preserve the clock signal to the shared component as long as at least one of the processor cores has not disabled the shared component. That is, to block the clock signal to the shared component, each of the processor cores must disable the shared component. The shared component may, for example, be a shared program memory or an arbiter for an external input/output port. The clock tree may include a register and a series of clock gates. Each of the clock gates blocks the clock signal when a gate signal is de-asserted.

Abstract: A multi-core digital signal processor is disclosed having a shared program memory with conditional write protection. In one embodiment, the digital signal processor includes a shared program memory, an emulation logic module, and multiple processor cores each coupled to the shared program memory by corresponding instruction buses. The emulation logic module preferably determines the operating modes of each of the processors, e.g., whether they are operating in a normal mode or an emulation mode. In the emulation mode, the emulation logic can alter the states of various processor hardware and the contents of various registers and memory. The instruction buses each include a read/write signal that, while their corresponding processor cores are in normal mode, is maintained in a read state. On the other hand, when the processor cores are in the emulation mode, the processor cores are allowed to determine the state of the instruction bus read/write signals.

Abstract: A DSP device is disclosed having multiple DMA controllers with global DMA access to all volatile memory resources in the DSP device. In a preferred embodiment, each of the DMA controllers is coupled to each of the memory buses and is configured to control each of the memory buses. A memory bus multiplexer may be coupled between the subsystem memory bus and each of the DMA controllers, and an arbiter may be used to set the memory bus multiplexer so as to allow any one of the DMA controllers to control the memory bus. The memory bus may also be controlled by the host port interface via the memory bus multiplexer. A round-robin arbitration technique is used to provide each of the controllers and the host port interface fair access to the memory bus. This approach may advantageously provide increased flexibility in the use of DMA controllers to transfer data from place to place, with only a minimal increase in complexity.

Abstract: In order to sort signal group elements organized in blocks in a time-division multiplex protocol into frames of related elements, an address unit addresses the first element in each of the element blocks, then the second element in each element block, etc until all of the elements of all of the blocks have been addressed. In this manner, the related elements are sorted into frames of elements. The address unit performs this element sorting using a base address, an element index equal to the number of elements in a block, and a frame index equal to {the number of elements times (the number of frames minus one)} minus one as parameters.

Abstract: As the digital signal processor has become more flexible, the direct memory access controller has assumed greater computational power to permit the core processing unit to perform its specialized processing without responding to signal transfer requests. Not only does the direct memory access controller control the exchange of signal groups between the memory unit and the core processing unit, but the direct memory access controller is also responsible for the transfer of signal groups within the digital signal processor that originate from the serial port, and the interface unit (the unit that implements the direct transfer of signal groups from the memory unit of one digital signal processor to a second signal processor). The direct memory access controller has programmable channels that permit the signal group source component to be coupled to the signal group destination component. The address unit of the direct memory access unit must be able to accommodate a plurality of addressing modes.

Abstract: A microprocessor 1 is described which includes a multi-channel serial port (MCSP) 120. MCSP 120 includes clock generation and frame sync generation circuitry 300, multi-channel selection circuitry 310, and companding circuitry 320. The clock generation and frame sync generation circuitry is configurable by means of a Serial Port Control Register SPCR, and Receive Control Register RCR, a Transmit Control Register XCR, a Sample Rate Generator Register SRGR, and Pin Control Register PCR. The multi-channel selection circuitry is configurable by means of a Multi-Channel Register MCR, a Receive Channel Enable Register RCER and a Transmit Channel Enable Register XCER. Companding circuitry 320 performs optional expansion or compression of received or transmitted data using &mgr;-LAW or A-LAW, as selected by the Receive Control Register or the Transmit Control Register.

Abstract: A processing system comprises a digital signal processor (DSP) device and a host system on which the DSP device is implemented. The DSP device comprises a shared program memory and a plurality of processor subsystems coupled to the shared program memory to concurrently execute program instructions stored in the shared program memory. The host system is capable of independently debugging each subsystem. During debugging, the host device inserts breakpoints into the shared program memory and tracks the debug breakpoints to determine which subsystems are associated with the breakpoints. When a subsystem executes a breakpoint associated with that subsystem, the subsystem halts until the host gathers necessary debug information from the subsystem. However, when a subsystem executes a breakpoint that is not associated with that subsystem, the host system causes the subsystem to execute the original program instructions and proceed as directed.

Abstract: A DSP device is disclosed having multiple DMA controllers with global DMA access to all volatile memory resources in the DSP device. In a preferred embodiment, each of the DMA controllers is coupled to each of the memory buses and is configured to control each of the memory buses. A memory bus multiplexer may be coupled between the subsystem memory bus and each of the DMA controllers, and an arbiter may be used to set the memory bus multiplexer so as to allow any one of the DMA controllers to control the memory bus. The memory bus may also be controlled by the host port interface via the memory bus multiplexer. A round-robin arbitration technique is used to provide each of the controllers and the host port interface fair access to the memory bus. This approach may advantageously provide increased flexibility in the use of DMA controllers to transfer data from place to place, with only a minimal increase in complexity.

Abstract: A multi-core digital signal processor is disclosed having a shared program memory with conditional write protection. In one embodiment, the digital signal processor includes a shared program memory, an emulation logic module, and multiple processor cores each coupled to the shared program memory by corresponding instruction buses. The emulation logic module preferably determines the operating modes of each of the processors, e.g., whether they are operating in a normal mode or an emulation mode. In the emulation mode, the emulation logic can alter the states of various processor hardware and the contents of various registers and memory. The instruction buses each include a read/write signal that, while their corresponding processor cores are in normal mode, is maintained in a read state. On the other hand, when the processor cores are in the emulation mode, the processor cores are allowed to determine the state of the instruction bus read/write signals.

Abstract: A digital signal processing system is disclosed that includes multiple processor subsystems, an external input/output port (XPORT), and an XPORT arbiter. The processor subsystems each include a processor core and a DMA controller, both of which may require access to the XPORT. The XPORT arbiter grants access by separately arbitrating between the processor cores and between the DMA controllers, and further arbitrating between processor control or DMA control of the XPORT. Upon receiving a request signal from a DMA controller, the XPORT arbiter asserts a hold signal to each of the processor cores. The processor cores respond to the hold signal by asserting a hold acknowledge signal. Note that if a processor core is currently using the XPORT, the processor core will delay assertion of the hold acknowledge signal until it is through with the XPORT. The arbiter, after receiving assertions of each of the hold acknowledge signals, then asserts a grant signal to the DMA controller requesting access.

Abstract: A digital signal processing chip having a multiple processor cores with corresponding processor subsystems, a shared component, and a clock tree, is disclosed herein. A clock tree distributes clock signals to the processor cores and the shared component. The clock tree can be configured to disable one or more of the processor cores and the shared component by blocking the corresponding clock signal. This may advantageously conserve power. However, the clock tree is configured to preserve the clock signal to the shared component as long as at least one of the processor cores has not disabled the shared component. That is, to block the clock signal to the shared component, each of the processor cores must disable the shared component. The shared component may, for example, be a shared program memory or an arbiter for an external input/output port. The clock tree may include a register and a series of clock gates. Each of the clock gates blocks the clock signal when a gate signal is de-asserted.

Abstract: A bag and system for dispensing thermoplastic bags or the like from a stack of bags. The preferred, exemplary embodiment of the present system teaches a configuration which minimizes the probability of stress fractures in the dispensed bag, and tearing associated therewith, while providing a system which leaves no “throw away” product on the rack after dispensing a bag stack, as the present system has no central tear-off tab, thereby providing a more environmentally attractive alternative to other, prior art systems. Further, the bag of the present invention also contemplates a non-removable central mouth support raised area, wherein there is provided a support cut configured to accept a rack central support piece, the cut configured to provide maximum ease in separation of the dispensed bag from the pack, with clean separation of the area above the support cut of the pack, thereby preventing tearing of the bag upon dispensing.

Abstract: A microprocessor 1 is described which includes a multi-channel serial port (MCSP) 120. MCSP 120 includes clock generation and frame sync generation circuitry 300, multi-channel selection circuitry 310, and companding circuitry 320. The clock generation and frame sync generation circuitry is configurable by means of a Serial Port Control Register SPCR, and Receive Control Register RCR, a Transmit Control Register XCR, a Sample Rate Generator Register SRGR, and Pin Control Register PCR. The multi-channel selection circuitry is configurable by means of a Multi-Channel Register MCR, a Receive Channel Enable Register RCER and a Transmit Channel Enable Register XCER. Companding circuitry 320 performs optional expansion or compression of received or transmitted data using .mu.-LAW or A-LAW, as selected by the Receive Control Register or the Transmit Control Register.

Abstract: A bag and dispensing system system wherein the thermoplastic bag to be dispensed may be retained in an open position, to allow for the loading thereof with contents for carrying, such as purchased goods or the like. The system is further configured such that the loaded bag, when dispensed, draws the next bag in the stack forward into an open loading position such that it is ready to be loaded with goods without further manipulation by the attendant. The preferred embodiment of the present invention teaches the utilization multi-edged penetration punch applied to the handle area of the bags to hold said handles together for handling of the bag pack, and for facilitating opening of the next bag in the stack on the rack, when a loaded bag is removed.

Abstract: A bag and dispensing system system wherein the thermoplastic bag to be dispensed may be retained in an open position, to allow for the loading thereof with contents for carrying, such as purchased goods or the like. The system is further configured such that the loaded bag, when dispensed, draws the next bag in the stack forward into an open loading position such that it is ready to be loaded with goods without further manipulation by the attendant. The preferred embodiment of the present invention teaches the utilization multi-edged penetration punch applied to the handle area of the bags to hold said handles together for handling of the bag pack, and for facilitating opening of the next bag in the stack on the rack, when a loaded bag is removed.

Abstract: A bag and system for dispensing self-opening thermoplastic bags or the like from a stack of bags. The present system is configured such that it may be utilized with a variety of off-the-shelf rack configurations, and to provide optimal characteristics for dispensing bags one at a time, while further providing a system wherein the bag to be dispensed may be retained in an open position, to allow for the loading thereof with contents for carrying, such as purchased goods or the like. The system is further configured such that the loaded bag, when dispensed, draws the next bag in the stack forward into an open loading position such that it is ready to be loaded with goods without further manipulation by the attendant.

Abstract: A bag and system for dispensing self-opening thermoplastic bags or the like from a stack of bags. The present system is configured such that it may be utilized with a variety of off-the-shelf rack configurations, and to provide optimal characteristics for dispensing bags one at a time, while further providing a system wherein the bag to be dispensed may be retained in an open position, to allow for the loading thereof with contents for carrying, such as purchased goods or the like. The system is further configured such that the loaded bag, when dispensed, draws the next bag in the stack forward into an open loading position such that it is ready to be loaded with goods without further manipulation by the attendant.